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Srinivas Vamsi Parasa
committed
8367694: Fix jtreg test failure when Intel APX is enabled for KNL platforms
Reviewed-by: sviswanathan, epeter
1 parent c41add8 commit e883dec

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2 files changed

+24
-22
lines changed

2 files changed

+24
-22
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‎src/hotspot/cpu/x86/assembler_x86.cpp‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -13780,15 +13780,15 @@ void Assembler::pdepq(Register dst, Register src1, Address src2) {
1378013780

1378113781
void Assembler::sarxl(Register dst, Register src1, Register src2) {
1378213782
assert(VM_Version::supports_bmi2(), "");
13783-
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
13783+
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1378413784
int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes, true);
1378513785
emit_int16((unsigned char)0xF7, (0xC0 | encode));
1378613786
}
1378713787

1378813788
void Assembler::sarxl(Register dst, Address src1, Register src2) {
1378913789
assert(VM_Version::supports_bmi2(), "");
1379013790
InstructionMark im(this);
13791-
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
13791+
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1379213792
attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit);
1379313793
vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
1379413794
emit_int8((unsigned char)0xF7);
@@ -13797,15 +13797,15 @@ void Assembler::sarxl(Register dst, Address src1, Register src2) {
1379713797

1379813798
void Assembler::sarxq(Register dst, Register src1, Register src2) {
1379913799
assert(VM_Version::supports_bmi2(), "");
13800-
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
13800+
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1380113801
int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes, true);
1380213802
emit_int16((unsigned char)0xF7, (0xC0 | encode));
1380313803
}
1380413804

1380513805
void Assembler::sarxq(Register dst, Address src1, Register src2) {
1380613806
assert(VM_Version::supports_bmi2(), "");
1380713807
InstructionMark im(this);
13808-
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
13808+
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1380913809
attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit);
1381013810
vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
1381113811
emit_int8((unsigned char)0xF7);
@@ -13814,15 +13814,15 @@ void Assembler::sarxq(Register dst, Address src1, Register src2) {
1381413814

1381513815
void Assembler::shlxl(Register dst, Register src1, Register src2) {
1381613816
assert(VM_Version::supports_bmi2(), "");
13817-
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
13817+
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1381813818
int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes, true);
1381913819
emit_int16((unsigned char)0xF7, (0xC0 | encode));
1382013820
}
1382113821

1382213822
void Assembler::shlxl(Register dst, Address src1, Register src2) {
1382313823
assert(VM_Version::supports_bmi2(), "");
1382413824
InstructionMark im(this);
13825-
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
13825+
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1382613826
attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit);
1382713827
vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1382813828
emit_int8((unsigned char)0xF7);
@@ -13831,15 +13831,15 @@ void Assembler::shlxl(Register dst, Address src1, Register src2) {
1383113831

1383213832
void Assembler::shlxq(Register dst, Register src1, Register src2) {
1383313833
assert(VM_Version::supports_bmi2(), "");
13834-
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
13834+
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1383513835
int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes, true);
1383613836
emit_int16((unsigned char)0xF7, (0xC0 | encode));
1383713837
}
1383813838

1383913839
void Assembler::shlxq(Register dst, Address src1, Register src2) {
1384013840
assert(VM_Version::supports_bmi2(), "");
1384113841
InstructionMark im(this);
13842-
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
13842+
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1384313843
attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit);
1384413844
vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1384513845
emit_int8((unsigned char)0xF7);
@@ -13848,15 +13848,15 @@ void Assembler::shlxq(Register dst, Address src1, Register src2) {
1384813848

1384913849
void Assembler::shrxl(Register dst, Register src1, Register src2) {
1385013850
assert(VM_Version::supports_bmi2(), "");
13851-
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
13851+
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1385213852
int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes, true);
1385313853
emit_int16((unsigned char)0xF7, (0xC0 | encode));
1385413854
}
1385513855

1385613856
void Assembler::shrxl(Register dst, Address src1, Register src2) {
1385713857
assert(VM_Version::supports_bmi2(), "");
1385813858
InstructionMark im(this);
13859-
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
13859+
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1386013860
attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit);
1386113861
vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
1386213862
emit_int8((unsigned char)0xF7);
@@ -13865,15 +13865,15 @@ void Assembler::shrxl(Register dst, Address src1, Register src2) {
1386513865

1386613866
void Assembler::shrxq(Register dst, Register src1, Register src2) {
1386713867
assert(VM_Version::supports_bmi2(), "");
13868-
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
13868+
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1386913869
int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes, true);
1387013870
emit_int16((unsigned char)0xF7, (0xC0 | encode));
1387113871
}
1387213872

1387313873
void Assembler::shrxq(Register dst, Address src1, Register src2) {
1387413874
assert(VM_Version::supports_bmi2(), "");
1387513875
InstructionMark im(this);
13876-
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
13876+
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1387713877
attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit);
1387813878
vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
1387913879
emit_int8((unsigned char)0xF7);

‎src/hotspot/cpu/x86/vm_version_x86.cpp‎

Lines changed: 12 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1016,16 +1016,6 @@ void VM_Version::get_processor_features() {
10161016
_features.clear_feature(CPU_AVX10_2);
10171017
}
10181018

1019-
// Currently APX support is only enabled for targets supporting AVX512VL feature.
1020-
bool apx_supported = os_supports_apx_egprs() && supports_apx_f() && supports_avx512vl();
1021-
if (UseAPX && !apx_supported) {
1022-
warning("UseAPX is not supported on this CPU, setting it to false");
1023-
FLAG_SET_DEFAULT(UseAPX, false);
1024-
}
1025-
1026-
if (!UseAPX) {
1027-
_features.clear_feature(CPU_APX_F);
1028-
}
10291019

10301020
if (UseAVX < 2) {
10311021
_features.clear_feature(CPU_AVX2);
@@ -1049,6 +1039,7 @@ void VM_Version::get_processor_features() {
10491039
_features.clear_feature(CPU_VZEROUPPER);
10501040
_features.clear_feature(CPU_AVX512BW);
10511041
_features.clear_feature(CPU_AVX512VL);
1042+
_features.clear_feature(CPU_APX_F);
10521043
_features.clear_feature(CPU_AVX512DQ);
10531044
_features.clear_feature(CPU_AVX512_VNNI);
10541045
_features.clear_feature(CPU_AVX512_VAES);
@@ -1068,6 +1059,17 @@ void VM_Version::get_processor_features() {
10681059
}
10691060
}
10701061

1062+
// Currently APX support is only enabled for targets supporting AVX512VL feature.
1063+
bool apx_supported = os_supports_apx_egprs() && supports_apx_f() && supports_avx512vl();
1064+
if (UseAPX && !apx_supported) {
1065+
warning("UseAPX is not supported on this CPU, setting it to false");
1066+
FLAG_SET_DEFAULT(UseAPX, false);
1067+
}
1068+
1069+
if (!UseAPX) {
1070+
_features.clear_feature(CPU_APX_F);
1071+
}
1072+
10711073
if (FLAG_IS_DEFAULT(IntelJccErratumMitigation)) {
10721074
_has_intel_jcc_erratum = compute_has_intel_jcc_erratum();
10731075
FLAG_SET_ERGO(IntelJccErratumMitigation, _has_intel_jcc_erratum);

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