8352022: RISC-V: Support Zfa fminm_h/fmaxm_h for float16

Reviewed-by: fyang, mli

Author: Anjian-Wen

src/hotspot/cpu/riscv/assembler_riscv.hpp

@@ -1450,6 +1450,16 @@ enum operand_size { int8, int16, int32, uint32, int64 };
     fp_base<D_64_dp, 0b11110>(Rd, Rs1, 0b00001, 0b000);
   }
 
+  void fminm_h(FloatRegister Rd, FloatRegister Rs1, FloatRegister Rs2) {
+    assert_cond(UseZfa);
+    fp_base<H_16_hp, 0b00101>(Rd, Rs1, Rs2, 0b010);
+  }
+
+  void fmaxm_h(FloatRegister Rd, FloatRegister Rs1, FloatRegister Rs2) {
+    assert_cond(UseZfa);
+    fp_base<H_16_hp, 0b00101>(Rd, Rs1, Rs2, 0b011);
+  }
+
   void fminm_s(FloatRegister Rd, FloatRegister Rs1, FloatRegister Rs2) {
     assert_cond(UseZfa);
     fp_base<S_32_sp, 0b00101>(Rd, Rs1, Rs2, 0b010);

src/hotspot/cpu/riscv/riscv.ad

@@ -8386,6 +8386,7 @@ instruct binOps_HF_reg(fRegF dst, fRegF src1, fRegF src2)
 
 instruct min_max_HF_reg(fRegF dst, fRegF src1, fRegF src2)
 %{
+  predicate(!UseZfa);
   match(Set dst (MinHF src1 src2));
   match(Set dst (MaxHF src1 src2));
   format %{ "min_max_hf $dst, $src1, $src2" %}
@@ -8404,6 +8405,36 @@ instruct min_max_HF_reg(fRegF dst, fRegF src1, fRegF src2)
   ins_pipe(pipe_class_default);
 %}
 
+instruct minHF_reg_zfa(fRegF dst, fRegF src1, fRegF src2)
+%{
+  predicate(UseZfa);
+  match(Set dst (MinHF src1 src2));
+
+  format %{ "min_hf $dst, $src1, $src2" %}
+
+  ins_encode %{
+    __ fminm_h(as_FloatRegister($dst$$reg),
+               as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct maxHF_reg_zfa(fRegF dst, fRegF src1, fRegF src2)
+%{
+  predicate(UseZfa);
+  match(Set dst (MaxHF src1 src2));
+
+  format %{ "max_hf $dst, $src1, $src2" %}
+
+  ins_encode %{
+    __ fmaxm_h(as_FloatRegister($dst$$reg),
+               as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
 instruct fma_HF_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3)
 %{
   match(Set dst (FmaHF src3 (Binary src1 src2)));