@@ -10410,6 +10410,26 @@ void Assembler::vzeroupper_uncached() {
1041010410 }
1041110411}
1041210412
10413+ void Assembler::vfpclassss(KRegister kdst, XMMRegister src, uint8_t imm8) {
10414+ // Encoding: EVEX.LIG.66.0F3A.W0 67 /r ib
10415+ assert(VM_Version::supports_evex(), "");
10416+ assert(VM_Version::supports_avx512dq(), "");
10417+ InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
10418+ attributes.set_is_evex_instruction();
10419+ int encode = vex_prefix_and_encode(kdst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10420+ emit_int24((unsigned char)0x67, (unsigned char)(0xC0 | encode), imm8);
10421+ }
10422+
10423+ void Assembler::vfpclasssd(KRegister kdst, XMMRegister src, uint8_t imm8) {
10424+ // Encoding: EVEX.LIG.66.0F3A.W1 67 /r ib
10425+ assert(VM_Version::supports_evex(), "");
10426+ assert(VM_Version::supports_avx512dq(), "");
10427+ InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
10428+ attributes.set_is_evex_instruction();
10429+ int encode = vex_prefix_and_encode(kdst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10430+ emit_int24((unsigned char)0x67, (unsigned char)(0xC0 | encode), imm8);
10431+ }
10432+
1041310433void Assembler::fld_x(Address adr) {
1041410434 InstructionMark im(this);
1041510435 emit_int8((unsigned char)0xDB);
0 commit comments