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‎src/hotspot/cpu/aarch64/aarch64.ad‎

Lines changed: 8 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
//
22
// Copyright (c) 2003, 2021, Oracle and/or its affiliates. All rights reserved.
3-
// Copyright (c) 2014, 2020, Red Hat, Inc. All rights reserved.
3+
// Copyright (c) 2014, 2021, Red Hat, Inc. All rights reserved.
44
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
55
//
66
// This code is free software; you can redistribute it and/or modify it
@@ -1916,7 +1916,7 @@ void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
19161916
__ bind(L_skip_barrier);
19171917
}
19181918

1919-
if (UseSVE > 0 && C->max_vector_size() >= 16) {
1919+
if (C->max_vector_size() >= 16) {
19201920
__ reinitialize_ptrue();
19211921
}
19221922

@@ -3798,11 +3798,9 @@ encode %{
37983798
}
37993799
}
38003800

3801-
if (UseSVE > 0 && Compile::current()->max_vector_size() >= 16) {
3802-
// Only non uncommon_trap calls need to reinitialize ptrue.
3803-
if (uncommon_trap_request() == 0) {
3804-
__ reinitialize_ptrue();
3805-
}
3801+
// Only non uncommon_trap calls need to reinitialize ptrue.
3802+
if (Compile::current()->max_vector_size() >= 16 && uncommon_trap_request() == 0) {
3803+
__ reinitialize_ptrue();
38063804
}
38073805
%}
38083806

@@ -3813,7 +3811,7 @@ encode %{
38133811
if (call == NULL) {
38143812
ciEnv::current()->record_failure("CodeCache is full");
38153813
return;
3816-
} else if (UseSVE > 0 && Compile::current()->max_vector_size() >= 16) {
3814+
} else if (Compile::current()->max_vector_size() >= 16) {
38173815
__ reinitialize_ptrue();
38183816
}
38193817
%}
@@ -3851,7 +3849,7 @@ encode %{
38513849
__ bind(retaddr);
38523850
__ add(sp, sp, 2 * wordSize);
38533851
}
3854-
if (UseSVE > 0 && Compile::current()->max_vector_size() >= 16) {
3852+
if (Compile::current()->max_vector_size() >= 16) {
38553853
__ reinitialize_ptrue();
38563854
}
38573855
%}
@@ -3864,7 +3862,7 @@ encode %{
38643862
enc_class aarch64_enc_ret() %{
38653863
C2_MacroAssembler _masm(&cbuf);
38663864
#ifdef ASSERT
3867-
if (UseSVE > 0 && Compile::current()->max_vector_size() >= 16) {
3865+
if (Compile::current()->max_vector_size() >= 16) {
38683866
__ verify_ptrue();
38693867
}
38703868
#endif

‎src/hotspot/cpu/aarch64/aarch64_neon.ad‎

Lines changed: 12 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
1-
// Copyright (c) 2020, Oracle and/or its affiliates. All rights reserved.
2-
// Copyright (c) 2020, Arm Limited. All rights reserved.
1+
// Copyright (c) 2020, 2021, Oracle and/or its affiliates. All rights reserved.
2+
// Copyright (c) 2020, 2021, Arm Limited. All rights reserved.
33
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
//
55
// This code is free software; you can redistribute it and/or modify it
@@ -84,9 +84,11 @@ instruct reinterpretD2X(vecX dst, vecD src)
8484
n->in(1)->bottom_type()->is_vect()->length_in_bytes() == 8);
8585
match(Set dst (VectorReinterpret src));
8686
ins_cost(INSN_COST);
87-
format %{ " # reinterpret $dst,$src" %}
87+
format %{ " # reinterpret $dst,$src\t# D2X" %}
8888
ins_encode %{
89-
// If register is the same, then move is not needed.
89+
// If registers are the same, no register move is required - the
90+
// upper 64 bits of 'src' are expected to have been initialized
91+
// to zero.
9092
if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
9193
__ orr(as_FloatRegister($dst$$reg), __ T8B,
9294
as_FloatRegister($src$$reg),
@@ -102,14 +104,13 @@ instruct reinterpretX2D(vecD dst, vecX src)
102104
n->in(1)->bottom_type()->is_vect()->length_in_bytes() == 16);
103105
match(Set dst (VectorReinterpret src));
104106
ins_cost(INSN_COST);
105-
format %{ " # reinterpret $dst,$src" %}
107+
format %{ " # reinterpret $dst,$src\t# X2D" %}
106108
ins_encode %{
107-
// If register is the same, then move is not needed.
108-
if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
109-
__ orr(as_FloatRegister($dst$$reg), __ T8B,
110-
as_FloatRegister($src$$reg),
111-
as_FloatRegister($src$$reg));
112-
}
109+
// Resize the vector from 128-bits to 64-bits. The higher 64-bits of
110+
// the "dst" register must be cleared to zero.
111+
__ orr(as_FloatRegister($dst$$reg), __ T8B,
112+
as_FloatRegister($src$$reg),
113+
as_FloatRegister($src$$reg));
113114
%}
114115
ins_pipe(vlogical64);
115116
%}

‎src/hotspot/cpu/aarch64/aarch64_neon_ad.m4‎

Lines changed: 28 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
1-
// Copyright (c) 2020, Oracle and/or its affiliates. All rights reserved.
2-
// Copyright (c) 2020, Arm Limited. All rights reserved.
1+
// Copyright (c) 2020, 2021, Oracle and/or its affiliates. All rights reserved.
2+
// Copyright (c) 2020, 2021, Arm Limited. All rights reserved.
33
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
//
55
// This code is free software; you can redistribute it and/or modify it
@@ -97,28 +97,43 @@ dnl $1 $2
9797
REINTERPRET(D, 8)
9898
REINTERPRET(X, 16)
9999
dnl
100-
define(`REINTERPRET_X', `
101-
instruct reinterpret$1`'2$2`'(vec$2 dst, vec$1 src)
100+
101+
instruct reinterpretD2X(vecX dst, vecD src)
102102
%{
103-
predicate(n->bottom_type()->is_vect()->length_in_bytes() == $3 &&
104-
n->in(1)->bottom_type()->is_vect()->length_in_bytes() == $4);
103+
predicate(n->bottom_type()->is_vect()->length_in_bytes() == 16 &&
104+
n->in(1)->bottom_type()->is_vect()->length_in_bytes() == 8);
105105
match(Set dst (VectorReinterpret src));
106106
ins_cost(INSN_COST);
107-
format %{ " # reinterpret $dst,$src" %}
107+
format %{ " # reinterpret $dst,$src\t# D2X" %}
108108
ins_encode %{
109-
// If register is the same, then move is not needed.
109+
// If registers are the same, no register move is required - the
110+
// upper 64 bits of 'src' are expected to have been initialized
111+
// to zero.
110112
if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
111113
__ orr(as_FloatRegister($dst$$reg), __ T8B,
112114
as_FloatRegister($src$$reg),
113115
as_FloatRegister($src$$reg));
114116
}
115117
%}
116118
ins_pipe(vlogical64);
117-
%}')dnl
118-
dnl $1 $2 $3 $4
119-
REINTERPRET_X(D, X, 16, 8)
120-
REINTERPRET_X(X, D, 8, 16)
121-
dnl
119+
%}
120+
121+
instruct reinterpretX2D(vecD dst, vecX src)
122+
%{
123+
predicate(n->bottom_type()->is_vect()->length_in_bytes() == 8 &&
124+
n->in(1)->bottom_type()->is_vect()->length_in_bytes() == 16);
125+
match(Set dst (VectorReinterpret src));
126+
ins_cost(INSN_COST);
127+
format %{ " # reinterpret $dst,$src\t# X2D" %}
128+
ins_encode %{
129+
// Resize the vector from 128-bits to 64-bits. The higher 64-bits of
130+
// the "dst" register must be cleared to zero.
131+
__ orr(as_FloatRegister($dst$$reg), __ T8B,
132+
as_FloatRegister($src$$reg),
133+
as_FloatRegister($src$$reg));
134+
%}
135+
ins_pipe(vlogical64);
136+
%}
122137

123138
// ------------------------------ Vector cast -------------------------------
124139
dnl

‎src/hotspot/cpu/aarch64/gc/z/zBarrierSetAssembler_aarch64.cpp‎

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2019, 2020, Oracle and/or its affiliates. All rights reserved.
2+
* Copyright (c) 2019, 2021, Oracle and/or its affiliates. All rights reserved.
33
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
*
55
* This code is free software; you can redistribute it and/or modify it
@@ -354,6 +354,10 @@ class ZSaveLiveRegisters {
354354
~ZSaveLiveRegisters() {
355355
// Restore registers
356356
__ pop_fp(_fp_regs, sp);
357+
358+
// External runtime call may clobber ptrue reg
359+
__ reinitialize_ptrue();
360+
357361
__ pop(_gp_regs, sp);
358362
}
359363
};
@@ -428,11 +432,6 @@ void ZBarrierSetAssembler::generate_c2_load_barrier_stub(MacroAssembler* masm, Z
428432
ZSetupArguments setup_arguments(masm, stub);
429433
__ mov(rscratch1, stub->slow_path());
430434
__ blr(rscratch1);
431-
if (UseSVE > 0) {
432-
// Reinitialize the ptrue predicate register, in case the external runtime
433-
// call clobbers ptrue reg, as we may return to SVE compiled code.
434-
__ reinitialize_ptrue();
435-
}
436435
}
437436
// Stub exit
438437
__ b(*stub->continuation());

‎src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp‎

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
22
* Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
3-
* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
3+
* Copyright (c) 2014, 2021, Red Hat Inc. All rights reserved.
44
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
55
*
66
* This code is free software; you can redistribute it and/or modify it
@@ -2663,6 +2663,8 @@ void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude) {
26632663
as_FloatRegister(i+3), T1D, Address(post(sp, 4 * wordSize)));
26642664
}
26652665

2666+
reinitialize_ptrue();
2667+
26662668
pop(call_clobbered_registers() - exclude, sp);
26672669
}
26682670

@@ -2699,6 +2701,11 @@ void MacroAssembler::pop_CPU_state(bool restore_vectors, bool use_sve,
26992701
ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
27002702
as_FloatRegister(i+3), restore_vectors ? T2D : T1D, Address(post(sp, step)));
27012703
}
2704+
2705+
if (restore_vectors) {
2706+
reinitialize_ptrue();
2707+
}
2708+
27022709
pop(0x3fffffff, sp); // integer registers except lr & sp
27032710
}
27042711

@@ -5309,7 +5316,9 @@ void MacroAssembler::verify_sve_vector_length() {
53095316

53105317
void MacroAssembler::verify_ptrue() {
53115318
Label verify_ok;
5312-
assert(UseSVE > 0, "should only be used for SVE");
5319+
if (!UseSVE) {
5320+
return;
5321+
}
53135322
sve_cntp(rscratch1, B, ptrue, ptrue); // get true elements count.
53145323
sve_dec(rscratch1, B);
53155324
cbz(rscratch1, verify_ok);

‎src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp‎

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
2-
* Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
3-
* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
2+
* Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
3+
* Copyright (c) 2014, 2021, Red Hat Inc. All rights reserved.
44
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
55
*
66
* This code is free software; you can redistribute it and/or modify it
@@ -967,7 +967,9 @@ class MacroAssembler: public Assembler {
967967

968968
void verify_sve_vector_length();
969969
void reinitialize_ptrue() {
970-
sve_ptrue(ptrue, B);
970+
if (UseSVE > 0) {
971+
sve_ptrue(ptrue, B);
972+
}
971973
}
972974
void verify_ptrue();
973975

‎src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp‎

Lines changed: 4 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
22
* Copyright (c) 2003, 2021, Oracle and/or its affiliates. All rights reserved.
3-
* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
3+
* Copyright (c) 2014, 2021, Red Hat Inc. All rights reserved.
44
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
55
*
66
* This code is free software; you can redistribute it and/or modify it
@@ -2781,12 +2781,6 @@ SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, int poll_t
27812781

27822782
__ membar(Assembler::LoadLoad | Assembler::LoadStore);
27832783

2784-
if (UseSVE > 0 && save_vectors) {
2785-
// Reinitialize the ptrue predicate register, in case the external runtime
2786-
// call clobbers ptrue reg, as we may return to SVE compiled code.
2787-
__ reinitialize_ptrue();
2788-
}
2789-
27902784
__ ldr(rscratch1, Address(rthread, Thread::pending_exception_offset()));
27912785
__ cbz(rscratch1, noException);
27922786

@@ -3009,6 +3003,9 @@ void OptoRuntime::generate_exception_blob() {
30093003
// handle_exception_C is a special VM call which does not require an explicit
30103004
// instruction sync afterwards.
30113005

3006+
// May jump to SVE compiled code
3007+
__ reinitialize_ptrue();
3008+
30123009
// Set an oopmap for the call site. This oopmap will only be used if we
30133010
// are unwinding the stack. Hence, all locations will be dead.
30143011
// Callee-saved registers will be the same as the frame above (i.e.,

‎src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp‎

Lines changed: 8 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
22
* Copyright (c) 2003, 2021, Oracle and/or its affiliates. All rights reserved.
3-
* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
3+
* Copyright (c) 2014, 2021, Red Hat Inc. All rights reserved.
44
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
55
*
66
* This code is free software; you can redistribute it and/or modify it
@@ -490,11 +490,10 @@ class StubGenerator: public StubCodeGenerator {
490490
__ call_VM_leaf(CAST_FROM_FN_PTR(address,
491491
SharedRuntime::exception_handler_for_return_address),
492492
rthread, c_rarg1);
493-
if (UseSVE > 0 ) {
494-
// Reinitialize the ptrue predicate register, in case the external runtime
495-
// call clobbers ptrue reg, as we may return to SVE compiled code.
496-
__ reinitialize_ptrue();
497-
}
493+
// Reinitialize the ptrue predicate register, in case the external runtime
494+
// call clobbers ptrue reg, as we may return to SVE compiled code.
495+
__ reinitialize_ptrue();
496+
498497
// we should not really care that lr is no longer the callee
499498
// address. we saved the value the handler needs in r19 so we can
500499
// just copy it to r3. however, the C2 handler will push its own
@@ -5655,11 +5654,9 @@ class StubGenerator: public StubCodeGenerator {
56555654

56565655
__ reset_last_Java_frame(true);
56575656

5658-
if (UseSVE > 0) {
5659-
// Reinitialize the ptrue predicate register, in case the external runtime
5660-
// call clobbers ptrue reg, as we may return to SVE compiled code.
5661-
__ reinitialize_ptrue();
5662-
}
5657+
// Reinitialize the ptrue predicate register, in case the external runtime
5658+
// call clobbers ptrue reg, as we may return to SVE compiled code.
5659+
__ reinitialize_ptrue();
56635660

56645661
__ leave();
56655662

‎src/hotspot/share/ci/ciMethodData.cpp‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -203,7 +203,12 @@ void ciMethodData::load_data() {
203203
// _extra_data_size = extra_data_limit - extra_data_base
204204
// total_size = _data_size + _extra_data_size
205205
// args_data_limit = data_base + total_size - parameter_data_size
206+
207+
#ifndef ZERO
208+
// Some Zero platforms do not have expected alignment, and do not use
209+
// this code. static_assert would still fire and fail for them.
206210
static_assert(sizeof(_orig) % HeapWordSize == 0, "align");
211+
#endif
207212
Copy::disjoint_words_atomic((HeapWord*) &mdo->_compiler_counters,
208213
(HeapWord*) &_orig,
209214
sizeof(_orig) / HeapWordSize);

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