8287567: AArch64: Implement post-call NOPs

Reviewed-by: adinn, rbackman, dlong

Author: Andrew Haley

src/hotspot/cpu/aarch64/assembler_aarch64.hpp

@@ -794,7 +794,7 @@ class Assembler : public AbstractAssembler {
     starti;                                                             \
     f(opcode, 31, 29), f(0b100101, 28, 23), f(shift/16, 22, 21),        \
       f(imm, 20, 5);                                                    \
-    rf(Rd, 0);                                                          \
+    zrf(Rd, 0);                                                          \
   }
 
   INSN(movnw, 0b000);

src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp

@@ -844,6 +844,8 @@ void MacroAssembler::post_call_nop() {
   InstructionMark im(this);
   relocate(post_call_nop_Relocation::spec());
   nop();
+  movk(zr, 0);
+  movk(zr, 0);
 }
 
 // these are no-ops overridden by InterpreterMacroAssembler

src/hotspot/cpu/aarch64/nativeInst_aarch64.cpp

@@ -549,8 +549,24 @@ void NativePostCallNop::make_deopt() {
   NativeDeoptInstruction::insert(addr_at(0));
 }
 
+#ifndef PRODUCT
+static bool is_movk_to_zr(uint32_t insn) {
+  return ((insn & 0xffe0001f) == 0xf280001f);
+}
+#endif
+
 void NativePostCallNop::patch(jint diff) {
-  // unsupported for now
+#ifndef PRODUCT
+  assert(diff != 0, "must be");
+  uint32_t insn1 = uint_at(4);
+  uint32_t insn2 = uint_at(8);
+  assert (is_movk_to_zr(insn1) && is_movk_to_zr(insn2), "must be");
+#endif
+
+  uint32_t lo = diff & 0xffff;
+  uint32_t hi = (uint32_t)diff >> 16;
+  Instruction_aarch64::patch(addr_at(4), 20, 5, lo);
+  Instruction_aarch64::patch(addr_at(8), 20, 5, hi);
 }
 
 void NativeDeoptInstruction::verify() {

src/hotspot/cpu/aarch64/nativeInst_aarch64.hpp

@@ -666,10 +666,33 @@ inline NativeLdSt* NativeLdSt_at(address addr) {
   return (NativeLdSt*)addr;
 }
 
+// A NativePostCallNop takes the form of three instructions:
+//     nop; movk zr, lo; movk zr, hi
+//
+// The nop is patchable for a deoptimization trap. The two movk
+// instructions execute as nops but have a 16-bit payload in which we
+// can store an offset from the initial nop to the nmethod.
+
 class NativePostCallNop: public NativeInstruction {
 public:
-  bool check() const { return is_nop(); }
-  int displacement() const { return 0; }
+  bool check() const {
+    uint64_t insns = *(uint64_t*)addr_at(0);
+    // Check for two instructions: nop; movk zr, xx
+    // These instructions only ever appear together in a post-call
+    // NOP, so it's unnecessary to check that the third instruction is
+    // a MOVK as well.
+    return (insns & 0xffe0001fffffffff) == 0xf280001fd503201f;
+  }
+
+  jint displacement() const {
+    uint64_t movk_insns = *(uint64_t*)addr_at(4);
+    uint32_t lo = (movk_insns >> 5) & 0xffff;
+    uint32_t hi = (movk_insns >> (5 + 32)) & 0xffff;
+    uint32_t result = (hi << 16) | lo;
+
+    return (jint)result;
+  }
+
   void patch(jint diff);
   void make_deopt();
 };

src/hotspot/share/code/codeCache.inline.hpp

@@ -41,6 +41,7 @@ inline CodeBlob* CodeCache::find_blob_and_oopmap(void* pc, int& slot) {
     int offset = (nop->displacement() & 0xffffff);
     cb = (CodeBlob*) ((address) pc - offset);
     slot = ((nop->displacement() >> 24) & 0xff);
+    assert(cb == CodeCache::find_blob(pc), "must be");
   } else {
     cb = CodeCache::find_blob(pc);
     slot = -1;