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RealFYangRealFYang
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8295270: RISC-V: Clean up and refactoring for assembler functions
Reviewed-by: fjiang, yadongwang, shade
1 parent be3b335 commit 3d75e88

12 files changed

+751
-713
lines changed

‎src/hotspot/cpu/riscv/assembler_riscv.cpp‎

Lines changed: 0 additions & 261 deletions
Original file line numberDiff line numberDiff line change
@@ -40,267 +40,6 @@ int AbstractAssembler::code_fill_byte() {
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return 0;
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}
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43-
void Assembler::add(Register Rd, Register Rn, int64_t increment, Register temp) {
44-
if (is_imm_in_range(increment, 12, 0)) {
45-
addi(Rd, Rn, increment);
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} else {
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assert_different_registers(Rn, temp);
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li(temp, increment);
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add(Rd, Rn, temp);
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}
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}
52-
53-
void Assembler::addw(Register Rd, Register Rn, int32_t increment, Register temp) {
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if (is_imm_in_range(increment, 12, 0)) {
55-
addiw(Rd, Rn, increment);
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} else {
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assert_different_registers(Rn, temp);
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li(temp, increment);
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addw(Rd, Rn, temp);
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}
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}
62-
63-
void Assembler::sub(Register Rd, Register Rn, int64_t decrement, Register temp) {
64-
if (is_imm_in_range(-decrement, 12, 0)) {
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addi(Rd, Rn, -decrement);
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} else {
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assert_different_registers(Rn, temp);
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li(temp, decrement);
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sub(Rd, Rn, temp);
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}
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}
72-
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void Assembler::subw(Register Rd, Register Rn, int32_t decrement, Register temp) {
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if (is_imm_in_range(-decrement, 12, 0)) {
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addiw(Rd, Rn, -decrement);
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} else {
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assert_different_registers(Rn, temp);
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li(temp, decrement);
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subw(Rd, Rn, temp);
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}
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}
82-
83-
void Assembler::zext_w(Register Rd, Register Rs) {
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add_uw(Rd, Rs, zr);
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}
86-
87-
void Assembler::_li(Register Rd, int64_t imm) {
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// int64_t is in range 0x8000 0000 0000 0000 ~ 0x7fff ffff ffff ffff
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int shift = 12;
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int64_t upper = imm, lower = imm;
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// Split imm to a lower 12-bit sign-extended part and the remainder,
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// because addi will sign-extend the lower imm.
93-
lower = ((int32_t)imm << 20) >> 20;
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upper -= lower;
95-
96-
// Test whether imm is a 32-bit integer.
97-
if (!(((imm) & ~(int64_t)0x7fffffff) == 0 ||
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(((imm) & ~(int64_t)0x7fffffff) == ~(int64_t)0x7fffffff))) {
99-
while (((upper >> shift) & 1) == 0) { shift++; }
100-
upper >>= shift;
101-
li(Rd, upper);
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slli(Rd, Rd, shift);
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if (lower != 0) {
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addi(Rd, Rd, lower);
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}
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} else {
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// 32-bit integer
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Register hi_Rd = zr;
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if (upper != 0) {
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lui(Rd, (int32_t)upper);
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hi_Rd = Rd;
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}
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if (lower != 0 || hi_Rd == zr) {
114-
addiw(Rd, hi_Rd, lower);
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}
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}
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}
118-
119-
void Assembler::li64(Register Rd, int64_t imm) {
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// Load upper 32 bits. upper = imm[63:32], but if imm[31] == 1 or
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// (imm[31:20] == 0x7ff && imm[19] == 1), upper = imm[63:32] + 1.
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int64_t lower = imm & 0xffffffff;
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lower -= ((lower << 44) >> 44);
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int64_t tmp_imm = ((uint64_t)(imm & 0xffffffff00000000)) + (uint64_t)lower;
125-
int32_t upper = (tmp_imm - (int32_t)lower) >> 32;
126-
127-
// Load upper 32 bits
128-
int64_t up = upper, lo = upper;
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lo = (lo << 52) >> 52;
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up -= lo;
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up = (int32_t)up;
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lui(Rd, up);
133-
addi(Rd, Rd, lo);
134-
135-
// Load the rest 32 bits.
136-
slli(Rd, Rd, 12);
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addi(Rd, Rd, (int32_t)lower >> 20);
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slli(Rd, Rd, 12);
139-
lower = ((int32_t)imm << 12) >> 20;
140-
addi(Rd, Rd, lower);
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slli(Rd, Rd, 8);
142-
lower = imm & 0xff;
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addi(Rd, Rd, lower);
144-
}
145-
146-
void Assembler::li32(Register Rd, int32_t imm) {
147-
// int32_t is in range 0x8000 0000 ~ 0x7fff ffff, and imm[31] is the sign bit
148-
int64_t upper = imm, lower = imm;
149-
lower = (imm << 20) >> 20;
150-
upper -= lower;
151-
upper = (int32_t)upper;
152-
// lui Rd, imm[31:12] + imm[11]
153-
lui(Rd, upper);
154-
// use addiw to distinguish li32 to li64
155-
addiw(Rd, Rd, lower);
156-
}
157-
158-
#define INSN(NAME, REGISTER) \
159-
void Assembler::NAME(const address &dest, Register temp) { \
160-
assert_cond(dest != NULL); \
161-
int64_t distance = dest - pc(); \
162-
if (is_imm_in_range(distance, 20, 1)) { \
163-
jal(REGISTER, distance); \
164-
} else { \
165-
assert(temp != noreg, "temp must not be empty register!"); \
166-
int32_t offset = 0; \
167-
movptr(temp, dest, offset); \
168-
jalr(REGISTER, temp, offset); \
169-
} \
170-
} \
171-
void Assembler::NAME(Label &l, Register temp) { \
172-
jal(REGISTER, l, temp); \
173-
} \
174-
175-
INSN(j, x0);
176-
INSN(jal, x1);
177-
178-
#undef INSN
179-
180-
#define INSN(NAME, REGISTER) \
181-
void Assembler::NAME(Register Rs) { \
182-
jalr(REGISTER, Rs, 0); \
183-
}
184-
185-
INSN(jr, x0);
186-
INSN(jalr, x1);
187-
188-
#undef INSN
189-
190-
#define INSN(NAME, REGISTER) \
191-
void Assembler::NAME(const Address &adr, Register temp) { \
192-
switch (adr.getMode()) { \
193-
case Address::literal: { \
194-
relocate(adr.rspec()); \
195-
NAME(adr.target(), temp); \
196-
break; \
197-
} \
198-
case Address::base_plus_offset: { \
199-
int32_t offset = 0; \
200-
baseOffset(temp, adr, offset); \
201-
jalr(REGISTER, temp, offset); \
202-
break; \
203-
} \
204-
default: \
205-
ShouldNotReachHere(); \
206-
} \
207-
}
208-
209-
INSN(j, x0);
210-
INSN(jal, x1);
211-
212-
#undef INSN
213-
214-
void Assembler::wrap_label(Register r1, Register r2, Label &L, compare_and_branch_insn insn,
215-
compare_and_branch_label_insn neg_insn, bool is_far) {
216-
if (is_far) {
217-
Label done;
218-
(this->*neg_insn)(r1, r2, done, /* is_far */ false);
219-
j(L);
220-
bind(done);
221-
} else {
222-
if (L.is_bound()) {
223-
(this->*insn)(r1, r2, target(L));
224-
} else {
225-
L.add_patch_at(code(), locator());
226-
(this->*insn)(r1, r2, pc());
227-
}
228-
}
229-
}
230-
231-
void Assembler::wrap_label(Register Rt, Label &L, Register tmp, load_insn_by_temp insn) {
232-
if (L.is_bound()) {
233-
(this->*insn)(Rt, target(L), tmp);
234-
} else {
235-
L.add_patch_at(code(), locator());
236-
(this->*insn)(Rt, pc(), tmp);
237-
}
238-
}
239-
240-
void Assembler::wrap_label(Register Rt, Label &L, jal_jalr_insn insn) {
241-
if (L.is_bound()) {
242-
(this->*insn)(Rt, target(L));
243-
} else {
244-
L.add_patch_at(code(), locator());
245-
(this->*insn)(Rt, pc());
246-
}
247-
}
248-
249-
void Assembler::movptr(Register Rd, address addr, int32_t &offset) {
250-
int64_t imm64 = (int64_t)addr;
251-
#ifndef PRODUCT
252-
{
253-
char buffer[64];
254-
snprintf(buffer, sizeof(buffer), "0x%" PRIx64, imm64);
255-
block_comment(buffer);
256-
}
257-
#endif
258-
assert(is_unsigned_imm_in_range(imm64, 47, 0) || (imm64 == (int64_t)-1),
259-
"bit 47 overflows in address constant");
260-
// Load upper 31 bits
261-
int64_t imm = imm64 >> 17;
262-
int64_t upper = imm, lower = imm;
263-
lower = (lower << 52) >> 52;
264-
upper -= lower;
265-
upper = (int32_t)upper;
266-
lui(Rd, upper);
267-
addi(Rd, Rd, lower);
268-
269-
// Load the rest 17 bits.
270-
slli(Rd, Rd, 11);
271-
addi(Rd, Rd, (imm64 >> 6) & 0x7ff);
272-
slli(Rd, Rd, 6);
273-
274-
// This offset will be used by following jalr/ld.
275-
offset = imm64 & 0x3f;
276-
}
277-
278-
void Assembler::movptr(Register Rd, uintptr_t imm64) {
279-
movptr(Rd, (address)imm64);
280-
}
281-
282-
void Assembler::movptr(Register Rd, address addr) {
283-
int offset = 0;
284-
movptr(Rd, addr, offset);
285-
addi(Rd, Rd, offset);
286-
}
287-
288-
#define INSN(NAME, NEG_INSN) \
289-
void Assembler::NAME(Register Rs, Register Rt, const address &dest) { \
290-
NEG_INSN(Rt, Rs, dest); \
291-
} \
292-
void Assembler::NAME(Register Rs, Register Rt, Label &l, bool is_far) { \
293-
NEG_INSN(Rt, Rs, l, is_far); \
294-
}
295-
296-
INSN(bgt, blt);
297-
INSN(ble, bge);
298-
INSN(bgtu, bltu);
299-
INSN(bleu, bgeu);
300-
#undef INSN
301-
302-
#undef __
303-
30443
Address::Address(address target, relocInfo::relocType rtype) : _base(noreg), _offset(0), _mode(literal) {
30544
_target = target;
30645
switch (rtype) {

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