@@ -4250,16 +4250,6 @@ pipe_class ialu_reg_fat(rRegI dst)
42504250 ALU : S3; // any alu
42514251%}
42524252
4253- // Long ALU reg operation using big decoder
4254- pipe_class ialu_reg_long_fat(rRegL dst)
4255- %{
4256- instruction_count(2);
4257- dst : S4(write);
4258- dst : S3(read);
4259- D0 : S0(2); // big decoder only; twice
4260- ALU : S3(2); // any 2 alus
4261- %}
4262-
42634253// Integer ALU reg-reg operation
42644254pipe_class ialu_reg_reg(rRegI dst, rRegI src)
42654255%{
@@ -4270,16 +4260,6 @@ pipe_class ialu_reg_reg(rRegI dst, rRegI src)
42704260 ALU : S3; // any alu
42714261%}
42724262
4273- // Long ALU reg-reg operation
4274- pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
4275- %{
4276- instruction_count(2);
4277- dst : S4(write);
4278- src : S3(read);
4279- DECODE : S0(2); // any 2 decoders
4280- ALU : S3(2); // both alus
4281- %}
4282-
42834263// Integer ALU reg-reg operation
42844264pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
42854265%{
@@ -4290,16 +4270,6 @@ pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
42904270 ALU : S3; // any alu
42914271%}
42924272
4293- // Long ALU reg-reg operation
4294- pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
4295- %{
4296- instruction_count(2);
4297- dst : S4(write);
4298- src : S3(read);
4299- D0 : S0(2); // big decoder only; twice
4300- ALU : S3(2); // both alus
4301- %}
4302-
43034273// Integer ALU reg-mem operation
43044274pipe_class ialu_reg_mem(rRegI dst, memory mem)
43054275%{
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