diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/shannonization.sln b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/shannonization.sln index 1f04f6bd2c..6f05cff9e7 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/shannonization.sln +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/shannonization.sln @@ -3,9 +3,7 @@ Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio 15 VisualStudioVersion = 15.0.28307.705 MinimumVisualStudioVersion = 10.0.40219.1 -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "shannonization_a10", "shannonization_a10.vcxproj", "{D6A634E7-9F2B-46C2-A21C-2402F631A55A}" -EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "shannonization_s10", "shannonization_s10.vcxproj", "{30A42429-E56D-4448-903E-6F4C4756E491}" +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "shannonization", "shannonization.vcxproj", "{D6A634E7-9F2B-46C2-A21C-2402F631A55A}" EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/shannonization_a10.vcxproj b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/shannonization.vcxproj similarity index 97% rename from DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/shannonization_a10.vcxproj rename to DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/shannonization.vcxproj index 3befc5b9ec..0f770c2cd6 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/shannonization_a10.vcxproj +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/shannonization.vcxproj @@ -105,7 +105,6 @@ -DFPGA_EMULATOR %(AdditionalOptions) $(IntDir)shannonization.obj $(ONEAPI_ROOT)dev-utilities\latest\include - A10;%(PreprocessorDefinitions) Console @@ -147,7 +146,6 @@ -DFPGA_EMULATOR %(AdditionalOptions) $(IntDir)shannonization.obj $(ONEAPI_ROOT)dev-utilities\latest\include - A10;%(PreprocessorDefinitions) Console @@ -160,4 +158,4 @@ - \ No newline at end of file + diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/shannonization_s10.vcxproj b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/shannonization_s10.vcxproj deleted file mode 100755 index 52602f8900..0000000000 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/shannonization_s10.vcxproj +++ /dev/null @@ -1,166 +0,0 @@ - - - - - Debug - x64 - - - Release - x64 - - - - - S10;%(PreprocessorDefinitions) - S10;%(PreprocessorDefinitions) - - - - 15.0 - {30A42429-E56D-4448-903E-6F4C4756E491} - Win32Proj - join - 10.0.17763.0 - - - - Application - true - Intel(R) oneAPI DPC++ Compiler - Unicode - - - Application - false - Intel(R) oneAPI DPC++ Compiler - true - Unicode - - - Application - true - Intel(R) oneAPI DPC++ Compiler - Unicode - - - Application - false - Intel(R) oneAPI DPC++ Compiler - true - Unicode - - - - - - - - - - - - - - - - - - - - - true - - - true - - - false - - - false - - - - Use - Level3 - Disabled - true - true - pch.h - $(ONEAPI_ROOT)dev-utilities\latest\include - - - Console - true - -Xsboard=intel_s10sx_pac:pac_s10; -Xshyper-optimized-handshaking=off - - - - - Use - Level3 - Disabled - true - true - pch.h - true - -DFPGA_EMULATOR %(AdditionalOptions) - $(IntDir)shannonization.obj - $(ONEAPI_ROOT)dev-utilities\latest\include - S10;%(PreprocessorDefinitions) - - - Console - true - -Xsboard=intel_s10sx_pac:pac_s10; -Xshyper-optimized-handshaking=off - - - - - Use - Level3 - MaxSpeed - true - true - true - true - pch.h - $(ONEAPI_ROOT)dev-utilities\latest\include - - - Console - true - true - true - -Xsboard=intel_s10sx_pac:pac_s10; -Xshyper-optimized-handshaking=off - - - - - Use - Level3 - MaxSpeed - true - true - true - true - pch.h - true - -DFPGA_EMULATOR %(AdditionalOptions) - $(IntDir)shannonization.obj - $(ONEAPI_ROOT)dev-utilities\latest\include - S10;%(PreprocessorDefinitions) - - - Console - true - true - true - -Xsboard=intel_s10sx_pac:pac_s10; -Xshyper-optimized-handshaking=off - - - - - - \ No newline at end of file diff --git a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/src/shannonization.cpp b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/src/shannonization.cpp index 68da205152..d47f9795b8 100644 --- a/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/src/shannonization.cpp +++ b/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/shannonization/src/shannonization.cpp @@ -268,28 +268,28 @@ int main(int argc, char** argv) { bool success = true; - // Instantiate multiple versions of the kernel - // The II achieved by the compiler can differ between FPGA architectures - // - // On Arria 10, we are able to achieve an II of 1 for versions 1 and 2 of - // the kernel (not version 0). - // Version 2 of the kernel can achieve the highest Fmax with - // an II of 1 (and therefore has the highest throughput). - // Since this tutorial compiles to a single FPGA image, this is not - // reflected in the final design (that is, version 1 bottlenecks the Fmax - // of the entire design, which contains versions 0, 1 and 2). - // However, the difference between versions 1 and 2 - // can be seen in the "Block Scheduled Fmax" columns in the - // "Loop Analysis" tab of the HTML reports. - // - // On Stratix 10 and Agilex, the same discussion applies, but version 0 - // can only achieve an II of 3 while versions 1 and 2 can only achieve - // an II of 2. On Stratix 10 and Agilex, we can achieve an II of 1 if we use - // non-blocking pipe reads in the IntersectionKernel, which is shown in - // version 3 of the kernel. - // + // Instantiate multiple versions of the kernel + // The II achieved by the compiler can differ between FPGA architectures + // + // On Arria 10, we are able to achieve an II of 1 for all versions of the + // kernel. + // Version 2 of the kernel can achieve the highest Fmax with + // an II of 1 (and therefore has the highest throughput). + // Since this tutorial compiles to a single FPGA image, this is not + // reflected in the final design (that is, version 1 bottlenecks the Fmax + // of the entire design, which contains versions 0, 1 and 2). + // However, the difference between versions 1 and 2 + // can be seen in the "Block Scheduled Fmax" columns in the + // "Loop Analysis" tab of the HTML reports. + // + // On Stratix 10 and Agilex, the same discussion applies, but version 0 + // can only achieve an II of 3 while versions 1 and 2 can only achieve + // an II of 2. On Stratix 10 and Agilex, we can achieve an II of 1 if we use + // non-blocking pipe reads in the IntersectionKernel, which is shown in + // version 3 of the kernel. + // #if defined(A10) - success &= Intersection<0,2>(q, a, b, golden_n); + success &= Intersection<0,1>(q, a, b, golden_n); success &= Intersection<1,1>(q, a, b, golden_n); success &= Intersection<2,1>(q, a, b, golden_n); success &= Intersection<3,1>(q, a, b, golden_n);