From 656ee8ac50a4e4d6ff7be53603572a45eaca8408 Mon Sep 17 00:00:00 2001 From: Adam Kondraciuk Date: Tue, 28 Oct 2025 12:50:16 +0100 Subject: [PATCH 1/8] Revert "[nrf noup] soc/nordic/nrf54h20/pm_s2ram: extend mcuboot_resume_s" This reverts commit 079a5d605b34b995bd002561943547ad9cf5f17d. Signed-off-by: Adam Kondraciuk --- boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts | 8 ++++---- soc/nordic/nrf54h/pm_s2ram.h | 1 - 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts index e2d5b08cd300..6d403481ffcb 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts @@ -361,16 +361,16 @@ zephyr_udc0: &usbhs { }; /* temporary stack for S2RAM resume logic */ - pm_s2ram_stack: cpuapp_s2ram_stack@22007fc8 { + pm_s2ram_stack: cpuapp_s2ram_stack@22007fcc { compatible = "zephyr,memory-region", "mmio-sram"; - reg = <0x22007fc8 16>; + reg = <0x22007fcc 16>; zephyr,memory-region = "pm_s2ram_stack"; }; /* run-time common mcuboot S2RAM support section */ - mcuboot_s2ram: cpuapp_s2ram@22007fd8 { + mcuboot_s2ram: cpuapp_s2ram@22007fdc { compatible = "zephyr,memory-region", "mmio-sram"; - reg = <0x22007fd8 8>; + reg = <0x22007fdc 4>; zephyr,memory-region = "mcuboot_s2ram_context"; }; diff --git a/soc/nordic/nrf54h/pm_s2ram.h b/soc/nordic/nrf54h/pm_s2ram.h index 01c098ea4310..0906010cbe08 100644 --- a/soc/nordic/nrf54h/pm_s2ram.h +++ b/soc/nordic/nrf54h/pm_s2ram.h @@ -14,7 +14,6 @@ struct mcuboot_resume_s { uint32_t magic; /* magic value to identify valid structure */ - uint32_t slot_info; }; /** From 96013afdae86395e1fb06bdf1e6452f007cee45f Mon Sep 17 00:00:00 2001 From: Adam Kondraciuk Date: Tue, 28 Oct 2025 12:50:30 +0100 Subject: [PATCH 2/8] Revert "[nrf noup] soc/nordic/nrf54h/pm_s2ram: S2RAM resume hardening" This reverts commit 98bd8d2e46cb11c07bcaecc07729598537400b59. Signed-off-by: Adam Kondraciuk --- .../nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts | 13 +++---------- soc/nordic/nrf54h/pm_s2ram.c | 14 -------------- soc/nordic/nrf54h/pm_s2ram.h | 6 ------ 3 files changed, 3 insertions(+), 30 deletions(-) diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts index 6d403481ffcb..fa378bb0bc8b 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts @@ -361,21 +361,14 @@ zephyr_udc0: &usbhs { }; /* temporary stack for S2RAM resume logic */ - pm_s2ram_stack: cpuapp_s2ram_stack@22007fcc { + pm_s2ram_stack: cpuapp_s2ram_stack@22007fd0 { compatible = "zephyr,memory-region", "mmio-sram"; - reg = <0x22007fcc 16>; + reg = <0x22007fd0 16>; zephyr,memory-region = "pm_s2ram_stack"; }; - /* run-time common mcuboot S2RAM support section */ - mcuboot_s2ram: cpuapp_s2ram@22007fdc { - compatible = "zephyr,memory-region", "mmio-sram"; - reg = <0x22007fdc 4>; - zephyr,memory-region = "mcuboot_s2ram_context"; - }; - /* run-time common S2RAM cpu context RAM */ - pm_s2ram: cpuapp_s2ram@22007fe0 { + pm_s2ram: cpuapp_s2ram@22007fe0 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x22007fe0 32>; zephyr,memory-region = "pm_s2ram_context"; diff --git a/soc/nordic/nrf54h/pm_s2ram.c b/soc/nordic/nrf54h/pm_s2ram.c index 768233b2ac8b..753acdda6832 100644 --- a/soc/nordic/nrf54h/pm_s2ram.c +++ b/soc/nordic/nrf54h/pm_s2ram.c @@ -223,24 +223,10 @@ static void fpu_restore(_fpu_context_t *backup) #endif /* !defined(CONFIG_FPU_SHARING) */ #endif /* defined(CONFIG_FPU) */ -#if DT_NODE_EXISTS(DT_NODELABEL(mcuboot_s2ram)) &&\ - DT_NODE_HAS_COMPAT(DT_NODELABEL(mcuboot_s2ram), zephyr_memory_region) -/* Linker section name is given by `zephyr,memory-region` property of - * `zephyr,memory-region` compatible DT node with nodelabel `mcuboot_s2ram`. - */ -__attribute__((section(DT_PROP(DT_NODELABEL(mcuboot_s2ram), zephyr_memory_region)))) -volatile struct mcuboot_resume_s _mcuboot_resume; - -#define SET_MCUBOOT_RESUME_MAGIC() _mcuboot_resume.magic = MCUBOOT_S2RAM_RESUME_MAGIC -#else -#define SET_MCUBOOT_RESUME_MAGIC() -#endif - int soc_s2ram_suspend(pm_s2ram_system_off_fn_t system_off) { int ret; - SET_MCUBOOT_RESUME_MAGIC(); scb_save(&backup_data.scb_context); #if defined(CONFIG_FPU) #if !defined(CONFIG_FPU_SHARING) diff --git a/soc/nordic/nrf54h/pm_s2ram.h b/soc/nordic/nrf54h/pm_s2ram.h index 0906010cbe08..565afad6ca10 100644 --- a/soc/nordic/nrf54h/pm_s2ram.h +++ b/soc/nordic/nrf54h/pm_s2ram.h @@ -10,12 +10,6 @@ #ifndef _ZEPHYR_SOC_ARM_NORDIC_NRF_PM_S2RAM_H_ #define _ZEPHYR_SOC_ARM_NORDIC_NRF_PM_S2RAM_H_ -#define MCUBOOT_S2RAM_RESUME_MAGIC 0x75832419 - -struct mcuboot_resume_s { - uint32_t magic; /* magic value to identify valid structure */ -}; - /** * @brief Save CPU state on suspend * From 4d111ba1d0f869d2d4b00b288e8a44d75b2a89fa Mon Sep 17 00:00:00 2001 From: Rubin Gerritsen Date: Sat, 4 Oct 2025 14:50:48 +0200 Subject: [PATCH 3/8] [nrf fromtree] soc: nordic: nrf54h: s2ram: Use ARM MPU save/restore funcs This reduced the amount of duplicate code and unifies the code with other platforms. MPU retention was originally added in ee9d23945f18868196db0353e2879a955af2667d. Signed-off-by: Rubin Gerritsen (cherry picked from commit b45d7a8a626f3570de63f040efec93fddb40b0ec) --- soc/nordic/nrf54h/pm_s2ram.c | 80 ++++-------------------------------- 1 file changed, 7 insertions(+), 73 deletions(-) diff --git a/soc/nordic/nrf54h/pm_s2ram.c b/soc/nordic/nrf54h/pm_s2ram.c index 753acdda6832..bcdaf1629ef2 100644 --- a/soc/nordic/nrf54h/pm_s2ram.c +++ b/soc/nordic/nrf54h/pm_s2ram.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -22,16 +23,6 @@ #define SCnSCB_CPPWR_SU10_Pos 20U /*!< CPPWR: SU10 Position */ #define SCnSCB_CPPWR_SU10_Msk (1UL << SCnSCB_CPPWR_SU10_Pos) /*!< CPPWR: SU10 Mask */ -/* Currently dynamic regions are only used in case of userspace or stack guard and - * stack guard is not used by default on Cortex-M33 because there is a dedicated - * mechanism for stack overflow detection. Unless those condition change we don't - * need to store MPU content, it can just be reinitialized on resuming. - */ -#define MPU_USE_DYNAMIC_REGIONS IS_ENABLED(CONFIG_USERSPACE) || IS_ENABLED(CONFIG_MPU_STACK_GUARD) - -/* TODO: The num-mpu-regions property should be used. Needs to be added to dts bindings. */ -#define MPU_MAX_NUM_REGIONS 16 - typedef struct { /* NVIC components stored into RAM. */ uint32_t ISER[NVIC_MEMBER_SIZE(ISER)]; @@ -39,15 +30,6 @@ typedef struct { uint8_t IPR[NVIC_MEMBER_SIZE(IPR)]; } _nvic_context_t; -typedef struct { - uint32_t RNR; - uint32_t RBAR[MPU_MAX_NUM_REGIONS]; - uint32_t RLAR[MPU_MAX_NUM_REGIONS]; - uint32_t MAIR0; - uint32_t MAIR1; - uint32_t CTRL; -} _mpu_context_t; - typedef struct { uint32_t ICSR; uint32_t VTOR; @@ -76,8 +58,8 @@ typedef struct { struct backup { _nvic_context_t nvic_context; -#if defined(CONFIG_MPU) - _mpu_context_t mpu_context; +#if defined(CONFIG_ARM_MPU) + struct z_mpu_context_retained mpu_context; #endif _scb_context_t scb_context; #if defined(CONFIG_FPU) && !defined(CONFIG_FPU_SHARING) @@ -87,54 +69,6 @@ struct backup { static __noinit struct backup backup_data; -extern void z_arm_configure_static_mpu_regions(void); -extern int z_arm_mpu_init(void); - -#if defined(CONFIG_MPU) -/* MPU registers cannot be simply copied because content of RBARx RLARx registers - * depends on region which is selected by RNR register. - */ -static void mpu_save(_mpu_context_t *backup) -{ - if (!MPU_USE_DYNAMIC_REGIONS) { - return; - } - - backup->RNR = MPU->RNR; - - for (uint8_t i = 0; i < MPU_MAX_NUM_REGIONS; i++) { - MPU->RNR = i; - backup->RBAR[i] = MPU->RBAR; - backup->RLAR[i] = MPU->RLAR; - } - backup->MAIR0 = MPU->MAIR0; - backup->MAIR1 = MPU->MAIR1; - backup->CTRL = MPU->CTRL; -} - -static void mpu_restore(_mpu_context_t *backup) -{ - if (!MPU_USE_DYNAMIC_REGIONS) { - z_arm_mpu_init(); - z_arm_configure_static_mpu_regions(); - return; - } - - uint32_t rnr = backup->RNR; - - for (uint8_t i = 0; i < MPU_MAX_NUM_REGIONS; i++) { - MPU->RNR = i; - MPU->RBAR = backup->RBAR[i]; - MPU->RLAR = backup->RLAR[i]; - } - - MPU->MAIR0 = backup->MAIR0; - MPU->MAIR1 = backup->MAIR1; - MPU->RNR = rnr; - MPU->CTRL = backup->CTRL; -} -#endif /* defined(CONFIG_MPU) */ - static void nvic_save(_nvic_context_t *backup) { memcpy(backup->ISER, (uint32_t *)NVIC->ISER, sizeof(NVIC->ISER)); @@ -235,8 +169,8 @@ int soc_s2ram_suspend(pm_s2ram_system_off_fn_t system_off) fpu_power_down(); #endif nvic_save(&backup_data.nvic_context); -#if defined(CONFIG_MPU) - mpu_save(&backup_data.mpu_context); +#if defined(CONFIG_ARM_MPU) + z_arm_save_mpu_context(&backup_data.mpu_context); #endif ret = arch_pm_s2ram_suspend(system_off); /* Cache and FPU are powered down so power up is needed even if s2ram failed. */ @@ -252,8 +186,8 @@ int soc_s2ram_suspend(pm_s2ram_system_off_fn_t system_off) return ret; } -#if defined(CONFIG_MPU) - mpu_restore(&backup_data.mpu_context); +#if defined(CONFIG_ARM_MPU) + z_arm_restore_mpu_context(&backup_data.mpu_context); #endif nvic_restore(&backup_data.nvic_context); scb_restore(&backup_data.scb_context); From 6bba1af9a2e8414fa37e875de234373cd6f13922 Mon Sep 17 00:00:00 2001 From: Rubin Gerritsen Date: Sat, 4 Oct 2025 14:57:26 +0200 Subject: [PATCH 4/8] [nrf fromtree] soc: nordic: nrf54h: s2ram: Use ARM SCB save/restore funcs This reduced the amount of duplicate code and unifies the code with other platforms. With this change fewer registers are stored and restored. See also comment in scb.h for scb_context stating that only essential registers are stored and restored. No longer stored: - ICSR - SCR - CFSR - HFSR - DFSR - MMFAR - BFAR - AFSR No longer used: - SHPR[3..12]. This backup register was declared in the wrong way. In core_cm33.h and core_cm4.h this is declared as an array of 12 uint8_t's. That is 3 uint32_t's. Orignal SCB retention was added in 2055f7d5956aecf55c4babca22eadb23d59bc534. Signed-off-by: Rubin Gerritsen (cherry picked from commit 4c0d47857668b4d61a26ec04a39979d814a2bdee) --- soc/nordic/nrf54h/pm_s2ram.c | 62 +++--------------------------------- 1 file changed, 4 insertions(+), 58 deletions(-) diff --git a/soc/nordic/nrf54h/pm_s2ram.c b/soc/nordic/nrf54h/pm_s2ram.c index bcdaf1629ef2..59016597e0a2 100644 --- a/soc/nordic/nrf54h/pm_s2ram.c +++ b/soc/nordic/nrf54h/pm_s2ram.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -17,8 +18,6 @@ #define NVIC_MEMBER_SIZE(member) ARRAY_SIZE(((NVIC_Type *)0)->member) /* Coprocessor Power Control Register Definitions */ -#define SCnSCB_CPPWR_SU11_Pos 22U /*!< CPPWR: SU11 Position */ -#define SCnSCB_CPPWR_SU11_Msk (1UL << SCnSCB_CPPWR_SU11_Pos) /*!< CPPWR: SU11 Mask */ #define SCnSCB_CPPWR_SU10_Pos 20U /*!< CPPWR: SU10 Position */ #define SCnSCB_CPPWR_SU10_Msk (1UL << SCnSCB_CPPWR_SU10_Pos) /*!< CPPWR: SU10 Mask */ @@ -30,23 +29,6 @@ typedef struct { uint8_t IPR[NVIC_MEMBER_SIZE(IPR)]; } _nvic_context_t; -typedef struct { - uint32_t ICSR; - uint32_t VTOR; - uint32_t AIRCR; - uint32_t SCR; - uint32_t CCR; - uint32_t SHPR[12U]; - uint32_t SHCSR; - uint32_t CFSR; - uint32_t HFSR; - uint32_t DFSR; - uint32_t MMFAR; - uint32_t BFAR; - uint32_t AFSR; - uint32_t CPACR; -} _scb_context_t; - #if defined(CONFIG_FPU) && !defined(CONFIG_FPU_SHARING) typedef struct { uint32_t FPCCR; @@ -61,7 +43,7 @@ struct backup { #if defined(CONFIG_ARM_MPU) struct z_mpu_context_retained mpu_context; #endif - _scb_context_t scb_context; + struct scb_context scb_context; #if defined(CONFIG_FPU) && !defined(CONFIG_FPU_SHARING) _fpu_context_t fpu_context; #endif @@ -83,42 +65,6 @@ static void nvic_restore(_nvic_context_t *backup) memcpy((uint32_t *)NVIC->IPR, backup->IPR, sizeof(NVIC->IPR)); } -static void scb_save(_scb_context_t *backup) -{ - backup->ICSR = SCB->ICSR; - backup->VTOR = SCB->VTOR; - backup->AIRCR = SCB->AIRCR; - backup->SCR = SCB->SCR; - backup->CCR = SCB->CCR; - memcpy(backup->SHPR, (uint32_t *)SCB->SHPR, sizeof(SCB->SHPR)); - backup->SHCSR = SCB->SHCSR; - backup->CFSR = SCB->CFSR; - backup->HFSR = SCB->HFSR; - backup->DFSR = SCB->DFSR; - backup->MMFAR = SCB->MMFAR; - backup->BFAR = SCB->BFAR; - backup->AFSR = SCB->AFSR; - backup->CPACR = SCB->CPACR; -} - -static void scb_restore(_scb_context_t *backup) -{ - SCB->ICSR = backup->ICSR; - SCB->VTOR = backup->VTOR; - SCB->AIRCR = backup->AIRCR; - SCB->SCR = backup->SCR; - SCB->CCR = backup->CCR; - memcpy((uint32_t *)SCB->SHPR, backup->SHPR, sizeof(SCB->SHPR)); - SCB->SHCSR = backup->SHCSR; - SCB->CFSR = backup->CFSR; - SCB->HFSR = backup->HFSR; - SCB->DFSR = backup->DFSR; - SCB->MMFAR = backup->MMFAR; - SCB->BFAR = backup->BFAR; - SCB->AFSR = backup->AFSR; - SCB->CPACR = backup->CPACR; -} - #if defined(CONFIG_FPU) static void fpu_power_down(void) { @@ -161,7 +107,7 @@ int soc_s2ram_suspend(pm_s2ram_system_off_fn_t system_off) { int ret; - scb_save(&backup_data.scb_context); + z_arm_save_scb_context(&backup_data.scb_context); #if defined(CONFIG_FPU) #if !defined(CONFIG_FPU_SHARING) fpu_save(&backup_data.fpu_context); @@ -190,7 +136,7 @@ int soc_s2ram_suspend(pm_s2ram_system_off_fn_t system_off) z_arm_restore_mpu_context(&backup_data.mpu_context); #endif nvic_restore(&backup_data.nvic_context); - scb_restore(&backup_data.scb_context); + z_arm_restore_scb_context(&backup_data.scb_context); return ret; } From 41d23a91295bae5df55875318753f00a23556f49 Mon Sep 17 00:00:00 2001 From: Rubin Gerritsen Date: Sat, 4 Oct 2025 15:08:25 +0200 Subject: [PATCH 5/8] [nrf fromtree] soc: nordic: nrf54h: s2ram: Use ARM FPU save/restore funcs This reduced the amount of duplicate code and unifies the code with other platforms. With this change the caller and callee status registers are stored separately. Also, a different set of status registers are stored: - FPSCR instead of FPDSCR. FPDSCR contains the default values to be assigned to FPSCR when a new floating-point context is created. It therefore seems more correct to store the FPSCR. - FPCCR and FPCAR are no longer stored. FPU retention was originally added in: 8a5365c26c69c53c9800ae70498a0cde875d2726. Signed-off-by: Rubin Gerritsen (cherry picked from commit 43cd4caee84b1f0985e69b16115d75e552fcfcfb) --- soc/nordic/nrf54h/pm_s2ram.c | 39 ++++-------------------------------- 1 file changed, 4 insertions(+), 35 deletions(-) diff --git a/soc/nordic/nrf54h/pm_s2ram.c b/soc/nordic/nrf54h/pm_s2ram.c index 59016597e0a2..e06cb5138760 100644 --- a/soc/nordic/nrf54h/pm_s2ram.c +++ b/soc/nordic/nrf54h/pm_s2ram.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -19,9 +20,6 @@ /* Coprocessor Power Control Register Definitions */ -#define SCnSCB_CPPWR_SU10_Pos 20U /*!< CPPWR: SU10 Position */ -#define SCnSCB_CPPWR_SU10_Msk (1UL << SCnSCB_CPPWR_SU10_Pos) /*!< CPPWR: SU10 Mask */ - typedef struct { /* NVIC components stored into RAM. */ uint32_t ISER[NVIC_MEMBER_SIZE(ISER)]; @@ -29,15 +27,6 @@ typedef struct { uint8_t IPR[NVIC_MEMBER_SIZE(IPR)]; } _nvic_context_t; -#if defined(CONFIG_FPU) && !defined(CONFIG_FPU_SHARING) -typedef struct { - uint32_t FPCCR; - uint32_t FPCAR; - uint32_t FPDSCR; - uint32_t S[32]; -} _fpu_context_t; -#endif - struct backup { _nvic_context_t nvic_context; #if defined(CONFIG_ARM_MPU) @@ -45,7 +34,7 @@ struct backup { #endif struct scb_context scb_context; #if defined(CONFIG_FPU) && !defined(CONFIG_FPU_SHARING) - _fpu_context_t fpu_context; + struct fpu_ctx_full fpu_context; #endif }; @@ -81,26 +70,6 @@ static void fpu_power_up(void) __DSB(); __ISB(); } - -#if !defined(CONFIG_FPU_SHARING) -static void fpu_save(_fpu_context_t *backup) -{ - backup->FPCCR = FPU->FPCCR; - backup->FPCAR = FPU->FPCAR; - backup->FPDSCR = FPU->FPDSCR; - - __asm__ volatile("vstmia %0, {s0-s31}\n" : : "r"(backup->S) : "memory"); -} - -static void fpu_restore(_fpu_context_t *backup) -{ - FPU->FPCCR = backup->FPCCR; - FPU->FPCAR = backup->FPCAR; - FPU->FPDSCR = backup->FPDSCR; - - __asm__ volatile("vldmia %0, {s0-s31}\n" : : "r"(backup->S) : "memory"); -} -#endif /* !defined(CONFIG_FPU_SHARING) */ #endif /* defined(CONFIG_FPU) */ int soc_s2ram_suspend(pm_s2ram_system_off_fn_t system_off) @@ -110,7 +79,7 @@ int soc_s2ram_suspend(pm_s2ram_system_off_fn_t system_off) z_arm_save_scb_context(&backup_data.scb_context); #if defined(CONFIG_FPU) #if !defined(CONFIG_FPU_SHARING) - fpu_save(&backup_data.fpu_context); + z_arm_save_fp_context(&backup_data.fpu_context); #endif fpu_power_down(); #endif @@ -125,7 +94,7 @@ int soc_s2ram_suspend(pm_s2ram_system_off_fn_t system_off) fpu_power_up(); #if !defined(CONFIG_FPU_SHARING) /* Also the FPU content might be lost. */ - fpu_restore(&backup_data.fpu_context); + z_arm_restore_fp_context(&backup_data.fpu_context); #endif #endif if (ret < 0) { From 0fe90d60797a0d0282557ae518cb6531edfd95a3 Mon Sep 17 00:00:00 2001 From: Rubin Gerritsen Date: Tue, 28 Oct 2025 10:20:43 +0100 Subject: [PATCH 6/8] [nrf fromtree] soc: nordic: nrf54h: s2ram: Fix compiling with FPU This commit fixes a change introduced in #97025 where too many definitions where removed. Fixes issue #98382 Signed-off-by: Rubin Gerritsen (cherry picked from commit 499102fc471ec68a6da699c138bd2229d847460b) --- soc/nordic/nrf54h/pm_s2ram.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/soc/nordic/nrf54h/pm_s2ram.c b/soc/nordic/nrf54h/pm_s2ram.c index e06cb5138760..d8bb0fc4cd54 100644 --- a/soc/nordic/nrf54h/pm_s2ram.c +++ b/soc/nordic/nrf54h/pm_s2ram.c @@ -19,6 +19,11 @@ #define NVIC_MEMBER_SIZE(member) ARRAY_SIZE(((NVIC_Type *)0)->member) /* Coprocessor Power Control Register Definitions */ +#define SCnSCB_CPPWR_SU11_Pos 22U /*!< CPPWR: SU11 Position */ +#define SCnSCB_CPPWR_SU11_Msk (1UL << SCnSCB_CPPWR_SU11_Pos) /*!< CPPWR: SU11 Mask */ + +#define SCnSCB_CPPWR_SU10_Pos 20U /*!< CPPWR: SU10 Position */ +#define SCnSCB_CPPWR_SU10_Msk (1UL << SCnSCB_CPPWR_SU10_Pos) /*!< CPPWR: SU10 Mask */ typedef struct { /* NVIC components stored into RAM. */ From 6f0646fd33abd5f2ecd3c5fb7a2b78b77356d63c Mon Sep 17 00:00:00 2001 From: Andrzej Puzdrowski Date: Fri, 5 Sep 2025 18:11:52 +0200 Subject: [PATCH 7/8] [nrf noup] soc/nordic/nrf54h/pm_s2ram: S2RAM resume hardening Added support for hardening decision on resume from S2RAM by MCUboot bootloader. Application sets additional variable to MCUBOOT_S2RAM_RESUME_MAGIC which allows the bootloader to doublecheck. Signed-off-by: Andrzej Puzdrowski (cherry picked from commit d4bb1c6b9f1c941480a457b18ae36c9bdf49faa7) --- .../nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts | 13 ++++++++++--- soc/nordic/nrf54h/pm_s2ram.c | 14 ++++++++++++++ soc/nordic/nrf54h/pm_s2ram.h | 6 ++++++ 3 files changed, 30 insertions(+), 3 deletions(-) diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts index fa378bb0bc8b..6d403481ffcb 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts @@ -361,14 +361,21 @@ zephyr_udc0: &usbhs { }; /* temporary stack for S2RAM resume logic */ - pm_s2ram_stack: cpuapp_s2ram_stack@22007fd0 { + pm_s2ram_stack: cpuapp_s2ram_stack@22007fcc { compatible = "zephyr,memory-region", "mmio-sram"; - reg = <0x22007fd0 16>; + reg = <0x22007fcc 16>; zephyr,memory-region = "pm_s2ram_stack"; }; + /* run-time common mcuboot S2RAM support section */ + mcuboot_s2ram: cpuapp_s2ram@22007fdc { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x22007fdc 4>; + zephyr,memory-region = "mcuboot_s2ram_context"; + }; + /* run-time common S2RAM cpu context RAM */ - pm_s2ram: cpuapp_s2ram@22007fe0 { + pm_s2ram: cpuapp_s2ram@22007fe0 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x22007fe0 32>; zephyr,memory-region = "pm_s2ram_context"; diff --git a/soc/nordic/nrf54h/pm_s2ram.c b/soc/nordic/nrf54h/pm_s2ram.c index d8bb0fc4cd54..02103b117a68 100644 --- a/soc/nordic/nrf54h/pm_s2ram.c +++ b/soc/nordic/nrf54h/pm_s2ram.c @@ -77,11 +77,25 @@ static void fpu_power_up(void) } #endif /* defined(CONFIG_FPU) */ +#if DT_NODE_EXISTS(DT_NODELABEL(mcuboot_s2ram)) &&\ + DT_NODE_HAS_COMPAT(DT_NODELABEL(mcuboot_s2ram), zephyr_memory_region) +/* Linker section name is given by `zephyr,memory-region` property of + * `zephyr,memory-region` compatible DT node with nodelabel `mcuboot_s2ram`. + */ +__attribute__((section(DT_PROP(DT_NODELABEL(mcuboot_s2ram), zephyr_memory_region)))) +volatile struct mcuboot_resume_s _mcuboot_resume; + +#define SET_MCUBOOT_RESUME_MAGIC() _mcuboot_resume.magic = MCUBOOT_S2RAM_RESUME_MAGIC +#else +#define SET_MCUBOOT_RESUME_MAGIC() +#endif + int soc_s2ram_suspend(pm_s2ram_system_off_fn_t system_off) { int ret; z_arm_save_scb_context(&backup_data.scb_context); + SET_MCUBOOT_RESUME_MAGIC(); #if defined(CONFIG_FPU) #if !defined(CONFIG_FPU_SHARING) z_arm_save_fp_context(&backup_data.fpu_context); diff --git a/soc/nordic/nrf54h/pm_s2ram.h b/soc/nordic/nrf54h/pm_s2ram.h index 565afad6ca10..0906010cbe08 100644 --- a/soc/nordic/nrf54h/pm_s2ram.h +++ b/soc/nordic/nrf54h/pm_s2ram.h @@ -10,6 +10,12 @@ #ifndef _ZEPHYR_SOC_ARM_NORDIC_NRF_PM_S2RAM_H_ #define _ZEPHYR_SOC_ARM_NORDIC_NRF_PM_S2RAM_H_ +#define MCUBOOT_S2RAM_RESUME_MAGIC 0x75832419 + +struct mcuboot_resume_s { + uint32_t magic; /* magic value to identify valid structure */ +}; + /** * @brief Save CPU state on suspend * From 87fe4d91164cd653a302dfe5688da0fe11942371 Mon Sep 17 00:00:00 2001 From: Andrzej Puzdrowski Date: Tue, 30 Sep 2025 14:48:14 +0200 Subject: [PATCH 8/8] [nrf noup] soc/nordic/nrf54h20/pm_s2ram: extend mcuboot_resume_s nrf_squash! [nrf noup] soc/nordic/nf54h/pm_s2ram: S2RAM resume hardening Extended mcuboot_resume_s suture by slot_info field intended to be used by MCUboot for recognize proper boot slot in direct-xp mode. Signed-off-by: Andrzej Puzdrowski --- boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts | 8 ++++---- soc/nordic/nrf54h/pm_s2ram.h | 1 + 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts index 6d403481ffcb..e2d5b08cd300 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts @@ -361,16 +361,16 @@ zephyr_udc0: &usbhs { }; /* temporary stack for S2RAM resume logic */ - pm_s2ram_stack: cpuapp_s2ram_stack@22007fcc { + pm_s2ram_stack: cpuapp_s2ram_stack@22007fc8 { compatible = "zephyr,memory-region", "mmio-sram"; - reg = <0x22007fcc 16>; + reg = <0x22007fc8 16>; zephyr,memory-region = "pm_s2ram_stack"; }; /* run-time common mcuboot S2RAM support section */ - mcuboot_s2ram: cpuapp_s2ram@22007fdc { + mcuboot_s2ram: cpuapp_s2ram@22007fd8 { compatible = "zephyr,memory-region", "mmio-sram"; - reg = <0x22007fdc 4>; + reg = <0x22007fd8 8>; zephyr,memory-region = "mcuboot_s2ram_context"; }; diff --git a/soc/nordic/nrf54h/pm_s2ram.h b/soc/nordic/nrf54h/pm_s2ram.h index 0906010cbe08..01c098ea4310 100644 --- a/soc/nordic/nrf54h/pm_s2ram.h +++ b/soc/nordic/nrf54h/pm_s2ram.h @@ -14,6 +14,7 @@ struct mcuboot_resume_s { uint32_t magic; /* magic value to identify valid structure */ + uint32_t slot_info; }; /**