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| 1 | +// RUN: %clangxx -fsycl -fsycl-targets=%sycl_triple %s -o %t.out |
| 2 | +// RUN: %HOST_RUN_PLACEHOLDER %t.out |
| 3 | +// RUN: %CPU_RUN_PLACEHOLDER %t.out |
| 4 | +// RUN: %GPU_RUN_PLACEHOLDER %t.out |
| 5 | +// L0, OpenCL, and ROCm backends don't currently support |
| 6 | +// info::device::atomic_memory_order_capabilities and aspect::atomic64 |
| 7 | +// XFAIL: level_zero || opencl || rocm |
| 8 | + |
| 9 | +// NOTE: Tests load and store for supported memory orderings. |
| 10 | + |
| 11 | +#include <CL/sycl.hpp> |
| 12 | +#include <algorithm> |
| 13 | +#include <cassert> |
| 14 | +#include <numeric> |
| 15 | +#include <vector> |
| 16 | +using namespace sycl; |
| 17 | +using namespace sycl::ONEAPI; |
| 18 | + |
| 19 | +template <typename T, memory_order MO> class memory_order_kernel; |
| 20 | + |
| 21 | +template <typename T> void acq_rel_test(queue q, size_t N) { |
| 22 | + T a = 0; |
| 23 | + { |
| 24 | + buffer<T> a_buf(&a, 1); |
| 25 | + |
| 26 | + q.submit([&](handler &cgh) { |
| 27 | + auto a_acc = a_buf. template get_access<access::mode::read_write>(cgh); |
| 28 | + cgh.parallel_for<memory_order_kernel<T, memory_order::acq_rel>>( |
| 29 | + range<1>(N), [=](item<1> it) { |
| 30 | + int gid = it.get_id(0); |
| 31 | + auto aar = |
| 32 | + atomic_ref<T, memory_order::acq_rel, memory_scope::device, |
| 33 | + access::address_space::global_space>(a_acc[0]); |
| 34 | + auto ld = aar.load(); |
| 35 | + ld += 1; |
| 36 | + aar.store(ld); |
| 37 | + }); |
| 38 | + }); |
| 39 | + } |
| 40 | + |
| 41 | + // All work-items increment by 1, so final value should be equal to N |
| 42 | + assert(a == T(N)); |
| 43 | +} |
| 44 | + |
| 45 | +template <typename T> void seq_cst_test(queue q, size_t N) { |
| 46 | + T a = 0; |
| 47 | + T b = 0; |
| 48 | + { |
| 49 | + buffer<T> a_buf(&a, 1); |
| 50 | + buffer<T> b_buf(&b, 1); |
| 51 | + |
| 52 | + q.submit([&](handler &cgh) { |
| 53 | + auto a_acc = a_buf. template get_access<access::mode::read_write>(cgh); |
| 54 | + auto b_acc = b_buf. template get_access<access::mode::read_write>(cgh); |
| 55 | + cgh.parallel_for<memory_order_kernel<T, memory_order::seq_cst>>( |
| 56 | + range<1>(N), [=](item<1> it) { |
| 57 | + int gid = it.get_id(0); |
| 58 | + auto aar = |
| 59 | + atomic_ref<T, memory_order::seq_cst, memory_scope::device, |
| 60 | + access::address_space::global_space>(a_acc[0]); |
| 61 | + auto bar = |
| 62 | + atomic_ref<T, memory_order::seq_cst, memory_scope::device, |
| 63 | + access::address_space::global_space>(b_acc[0]); |
| 64 | + auto ald = aar.load(); |
| 65 | + auto bld = bar.load(); |
| 66 | + ald += 1; |
| 67 | + bld += ald; |
| 68 | + bar.store(bld); |
| 69 | + aar.store(ald); |
| 70 | + }); |
| 71 | + }); |
| 72 | + } |
| 73 | + |
| 74 | + // All work-items increment a by 1, so final value should be equal to N |
| 75 | + assert(a == T(N)); |
| 76 | + // b is the sum of [1..N] |
| 77 | + size_t rsum = 0; |
| 78 | + for (size_t i = 1; i <= N; ++i) |
| 79 | + rsum += i; |
| 80 | + assert(b == T(rsum)); |
| 81 | +} |
| 82 | + |
| 83 | +bool is_supported(std::vector<memory_order> capabilities, |
| 84 | + memory_order mem_order) { |
| 85 | + return std::find(capabilities.begin(), capabilities.end(), mem_order) != |
| 86 | + capabilities.end(); |
| 87 | +} |
| 88 | + |
| 89 | +int main() { |
| 90 | + queue q; |
| 91 | + |
| 92 | + std::vector<memory_order> supported_memory_orders = |
| 93 | + q.get_device().get_info<info::device::atomic_memory_order_capabilities>(); |
| 94 | + bool atomic64_support = q.get_device().has(aspect::atomic64); |
| 95 | + |
| 96 | + constexpr int N = 32; |
| 97 | + |
| 98 | + // Relaxed memory order must be supported. This ordering is used in other |
| 99 | + // tests. |
| 100 | + assert(is_supported(supported_memory_orders, memory_order::relaxed)); |
| 101 | + |
| 102 | + if (is_supported(supported_memory_orders, memory_order::acq_rel)) { |
| 103 | + // Acquire-release memory order must also support both acquire and release |
| 104 | + // orderings. |
| 105 | + assert(is_supported(supported_memory_orders, memory_order::acquire) && |
| 106 | + is_supported(supported_memory_orders, memory_order::release)); |
| 107 | + acq_rel_test<int>(q, N); |
| 108 | + acq_rel_test<unsigned int>(q, N); |
| 109 | + acq_rel_test<float>(q, N); |
| 110 | + if (sizeof(long) == 4) { |
| 111 | + // long is 32-bit |
| 112 | + acq_rel_test<long>(q, N); |
| 113 | + acq_rel_test<unsigned long>(q, N); |
| 114 | + } |
| 115 | + if (atomic64_support) { |
| 116 | + if (sizeof(long) == 8) { |
| 117 | + // long is 64-bit |
| 118 | + acq_rel_test<long>(q, N); |
| 119 | + acq_rel_test<unsigned long>(q, N); |
| 120 | + } |
| 121 | + acq_rel_test<long long>(q, N); |
| 122 | + acq_rel_test<unsigned long long>(q, N); |
| 123 | + acq_rel_test<double>(q, N); |
| 124 | + } |
| 125 | + } |
| 126 | + |
| 127 | + if (is_supported(supported_memory_orders, memory_order::seq_cst)) { |
| 128 | + seq_cst_test<int>(q, N); |
| 129 | + seq_cst_test<unsigned int>(q, N); |
| 130 | + seq_cst_test<float>(q, N); |
| 131 | + if (sizeof(long) == 4) { |
| 132 | + // long is 32-bit |
| 133 | + seq_cst_test<long>(q, N); |
| 134 | + seq_cst_test<unsigned long>(q, N); |
| 135 | + } |
| 136 | + if (atomic64_support) { |
| 137 | + if (sizeof(long) == 8) { |
| 138 | + // long is 64-bit |
| 139 | + seq_cst_test<long>(q, N); |
| 140 | + seq_cst_test<unsigned long>(q, N); |
| 141 | + } |
| 142 | + seq_cst_test<long long>(q, N); |
| 143 | + seq_cst_test<unsigned long long>(q, N); |
| 144 | + seq_cst_test<double>(q, N); |
| 145 | + } |
| 146 | + } |
| 147 | + |
| 148 | + std::cout << "Test passed." << std::endl; |
| 149 | +} |
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