diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h b/llvm/include/llvm/TargetParser/RISCVTargetParser.h index 7421dac2744b6..c75778952e0f5 100644 --- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h +++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h @@ -24,6 +24,14 @@ class Triple; namespace RISCV { +namespace RISCVExtensionBitmaskTable { +struct RISCVExtensionBitmask { + const char *Name; + unsigned GroupID; + unsigned BitPosition; +}; +} // namespace RISCVExtensionBitmaskTable + // We use 64 bits as the known part in the scalable vector types. static constexpr unsigned RVVBitsPerBlock = 64; diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index c9979b2b36fc3..c96d2dd83816b 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -37,6 +37,15 @@ class RISCVExtension groupID, int bitPos> { + int GroupID = groupID; + int BitPos = bitPos; +} + // Version of RISCVExtension to be used for Experimental extensions. This // sets the Experimental flag and prepends experimental- to the -mattr name. class RISCVExperimentalExtension; + "'I' (Base Integer Instruction Set)">, + RISCVExtensionBitmask<0, 8>; def FeatureStdExtE : RISCVExtension<"e", 2, 0, @@ -78,7 +88,8 @@ def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">, def FeatureStdExtZicboz : RISCVExtension<"zicboz", 1, 0, - "'Zicboz' (Cache-Block Zero Instructions)">; + "'Zicboz' (Cache-Block Zero Instructions)">, + RISCVExtensionBitmask<0, 37>; def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">, AssemblerPredicate<(all_of FeatureStdExtZicboz), "'Zicboz' (Cache-Block Zero Instructions)">; @@ -113,7 +124,8 @@ def FeatureStdExtZicntr def FeatureStdExtZicond : RISCVExtension<"zicond", 1, 0, - "'Zicond' (Integer Conditional Operations)">; + "'Zicond' (Integer Conditional Operations)">, + RISCVExtensionBitmask<0, 38>; def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">, AssemblerPredicate<(all_of FeatureStdExtZicond), "'Zicond' (Integer Conditional Operations)">; @@ -127,14 +139,16 @@ def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">, def FeatureStdExtZihintpause : RISCVExtension<"zihintpause", 2, 0, - "'Zihintpause' (Pause Hint)">; + "'Zihintpause' (Pause Hint)">, + RISCVExtensionBitmask<0, 40>; def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">, AssemblerPredicate<(all_of FeatureStdExtZihintpause), "'Zihintpause' (Pause Hint)">; def FeatureStdExtZihintntl : RISCVExtension<"zihintntl", 1, 0, - "'Zihintntl' (Non-Temporal Locality Hints)">; + "'Zihintntl' (Non-Temporal Locality Hints)">, + RISCVExtensionBitmask<0, 39>; def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">, AssemblerPredicate<(all_of FeatureStdExtZihintntl), "'Zihintntl' (Non-Temporal Locality Hints)">; @@ -181,7 +195,8 @@ def HasStdExtZmmul : Predicate<"Subtarget->hasStdExtZmmul()">, def FeatureStdExtM : RISCVExtension<"m", 2, 0, "'M' (Integer Multiplication and Division)", - [FeatureStdExtZmmul]>; + [FeatureStdExtZmmul]>, + RISCVExtensionBitmask<0, 12>; def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">, AssemblerPredicate<(all_of FeatureStdExtM), "'M' (Integer Multiplication and Division)">; @@ -190,14 +205,16 @@ def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">, def FeatureStdExtA : RISCVExtension<"a", 2, 1, - "'A' (Atomic Instructions)">; + "'A' (Atomic Instructions)">, + RISCVExtensionBitmask<0, 0>; def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">, AssemblerPredicate<(all_of FeatureStdExtA), "'A' (Atomic Instructions)">; def FeatureStdExtZtso : RISCVExtension<"ztso", 1, 0, - "'Ztso' (Memory Model - Total Store Order)">; + "'Ztso' (Memory Model - Total Store Order)">, + RISCVExtensionBitmask<0, 47>; def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">, AssemblerPredicate<(all_of FeatureStdExtZtso), "'Ztso' (Memory Model - Total Store Order)">; @@ -227,7 +244,8 @@ def HasStdExtZabha : Predicate<"Subtarget->hasStdExtZabha()">, def FeatureStdExtZacas : RISCVExtension<"zacas", 1, 0, - "'Zacas' (Atomic Compare-And-Swap Instructions)">; + "'Zacas' (Atomic Compare-And-Swap Instructions)">, + RISCVExtensionBitmask<0, 26>; def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">, AssemblerPredicate<(all_of FeatureStdExtZacas), "'Zacas' (Atomic Compare-And-Swap Instructions)">; @@ -264,7 +282,8 @@ def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">, def FeatureStdExtF : RISCVExtension<"f", 2, 2, "'F' (Single-Precision Floating-Point)", - [FeatureStdExtZicsr]>; + [FeatureStdExtZicsr]>, + RISCVExtensionBitmask<0, 5>; def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">, AssemblerPredicate<(all_of FeatureStdExtF), "'F' (Single-Precision Floating-Point)">; @@ -272,7 +291,8 @@ def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">, def FeatureStdExtD : RISCVExtension<"d", 2, 2, "'D' (Double-Precision Floating-Point)", - [FeatureStdExtF]>; + [FeatureStdExtF]>, + RISCVExtensionBitmask<0, 3>; def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">, AssemblerPredicate<(all_of FeatureStdExtD), "'D' (Double-Precision Floating-Point)">; @@ -280,7 +300,8 @@ def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">, def FeatureStdExtZfhmin : RISCVExtension<"zfhmin", 1, 0, "'Zfhmin' (Half-Precision Floating-Point Minimal)", - [FeatureStdExtF]>; + [FeatureStdExtF]>, + RISCVExtensionBitmask<0, 36>; def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">, AssemblerPredicate<(all_of FeatureStdExtZfhmin), "'Zfh' (Half-Precision Floating-Point) or " @@ -289,7 +310,8 @@ def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">, def FeatureStdExtZfh : RISCVExtension<"zfh", 1, 0, "'Zfh' (Half-Precision Floating-Point)", - [FeatureStdExtZfhmin]>; + [FeatureStdExtZfhmin]>, + RISCVExtensionBitmask<0, 35>; def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">, AssemblerPredicate<(all_of FeatureStdExtZfh), "'Zfh' (Half-Precision Floating-Point)">; @@ -313,7 +335,8 @@ def HasHalfFPLoadStoreMove def FeatureStdExtZfa : RISCVExtension<"zfa", 1, 0, "'Zfa' (Additional Floating-Point)", - [FeatureStdExtF]>; + [FeatureStdExtF]>, + RISCVExtensionBitmask<0, 34>; def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">, AssemblerPredicate<(all_of FeatureStdExtZfa), "'Zfa' (Additional Floating-Point)">; @@ -356,7 +379,8 @@ def NoStdExtZhinx : Predicate<"!Subtarget->hasStdExtZhinx()">; def FeatureStdExtC : RISCVExtension<"c", 2, 0, - "'C' (Compressed Instructions)">; + "'C' (Compressed Instructions)">, + RISCVExtensionBitmask<0, 2>; def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">, AssemblerPredicate<(all_of FeatureStdExtC), "'C' (Compressed Instructions)">; @@ -445,7 +469,8 @@ def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">, def FeatureStdExtZba : RISCVExtension<"zba", 1, 0, - "'Zba' (Address Generation Instructions)">; + "'Zba' (Address Generation Instructions)">, + RISCVExtensionBitmask<0, 27>; def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">, AssemblerPredicate<(all_of FeatureStdExtZba), "'Zba' (Address Generation Instructions)">; @@ -453,7 +478,8 @@ def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">; def FeatureStdExtZbb : RISCVExtension<"zbb", 1, 0, - "'Zbb' (Basic Bit-Manipulation)">; + "'Zbb' (Basic Bit-Manipulation)">, + RISCVExtensionBitmask<0, 28>; def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">, AssemblerPredicate<(all_of FeatureStdExtZbb), "'Zbb' (Basic Bit-Manipulation)">; @@ -462,14 +488,16 @@ def NoStdExtZbb : Predicate<"!Subtarget->hasStdExtZbb()">, def FeatureStdExtZbc : RISCVExtension<"zbc", 1, 0, - "'Zbc' (Carry-Less Multiplication)">; + "'Zbc' (Carry-Less Multiplication)">, + RISCVExtensionBitmask<0, 29>; def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">, AssemblerPredicate<(all_of FeatureStdExtZbc), "'Zbc' (Carry-Less Multiplication)">; def FeatureStdExtZbs : RISCVExtension<"zbs", 1, 0, - "'Zbs' (Single-Bit Instructions)">; + "'Zbs' (Single-Bit Instructions)">, + RISCVExtensionBitmask<0, 33>; def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">, AssemblerPredicate<(all_of FeatureStdExtZbs), "'Zbs' (Single-Bit Instructions)">; @@ -486,14 +514,16 @@ def HasStdExtB : Predicate<"Subtarget->hasStdExtB()">, def FeatureStdExtZbkb : RISCVExtension<"zbkb", 1, 0, - "'Zbkb' (Bitmanip instructions for Cryptography)">; + "'Zbkb' (Bitmanip instructions for Cryptography)">, + RISCVExtensionBitmask<0, 30>; def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">, AssemblerPredicate<(all_of FeatureStdExtZbkb), "'Zbkb' (Bitmanip instructions for Cryptography)">; def FeatureStdExtZbkx : RISCVExtension<"zbkx", 1, 0, - "'Zbkx' (Crossbar permutation instructions)">; + "'Zbkx' (Crossbar permutation instructions)">, + RISCVExtensionBitmask<0, 32>; def HasStdExtZbkx : Predicate<"Subtarget->hasStdExtZbkx()">, AssemblerPredicate<(all_of FeatureStdExtZbkx), "'Zbkx' (Crossbar permutation instructions)">; @@ -510,7 +540,8 @@ def HasStdExtZbbOrZbkb def FeatureStdExtZbkc : RISCVExtension<"zbkc", 1, 0, "'Zbkc' (Carry-less multiply instructions for " - "Cryptography)">; + "Cryptography)">, + RISCVExtensionBitmask<0, 31>; def HasStdExtZbkc : Predicate<"Subtarget->hasStdExtZbkc()">, AssemblerPredicate<(all_of FeatureStdExtZbkc), @@ -527,14 +558,16 @@ def HasStdExtZbcOrZbkc def FeatureStdExtZknd : RISCVExtension<"zknd", 1, 0, - "'Zknd' (NIST Suite: AES Decryption)">; + "'Zknd' (NIST Suite: AES Decryption)">, + RISCVExtensionBitmask<0, 41>; def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">, AssemblerPredicate<(all_of FeatureStdExtZknd), "'Zknd' (NIST Suite: AES Decryption)">; def FeatureStdExtZkne : RISCVExtension<"zkne", 1, 0, - "'Zkne' (NIST Suite: AES Encryption)">; + "'Zkne' (NIST Suite: AES Encryption)">, + RISCVExtensionBitmask<0, 42>; def HasStdExtZkne : Predicate<"Subtarget->hasStdExtZkne()">, AssemblerPredicate<(all_of FeatureStdExtZkne), "'Zkne' (NIST Suite: AES Encryption)">; @@ -549,21 +582,24 @@ def HasStdExtZkndOrZkne def FeatureStdExtZknh : RISCVExtension<"zknh", 1, 0, - "'Zknh' (NIST Suite: Hash Function Instructions)">; + "'Zknh' (NIST Suite: Hash Function Instructions)">, + RISCVExtensionBitmask<0, 43>; def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">, AssemblerPredicate<(all_of FeatureStdExtZknh), "'Zknh' (NIST Suite: Hash Function Instructions)">; def FeatureStdExtZksed : RISCVExtension<"zksed", 1, 0, - "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">; + "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">, + RISCVExtensionBitmask<0, 44>; def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">, AssemblerPredicate<(all_of FeatureStdExtZksed), "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">; def FeatureStdExtZksh : RISCVExtension<"zksh", 1, 0, - "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">; + "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">, + RISCVExtensionBitmask<0, 45>; def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">, AssemblerPredicate<(all_of FeatureStdExtZksh), "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">; @@ -596,7 +632,8 @@ def FeatureStdExtZks def FeatureStdExtZkt : RISCVExtension<"zkt", 1, 0, - "'Zkt' (Data Independent Execution Latency)">; + "'Zkt' (Data Independent Execution Latency)">, + RISCVExtensionBitmask<0, 46>; def FeatureStdExtZk : RISCVExtension<"zk", 1, 0, @@ -626,6 +663,7 @@ def FeatureStdExtZve32x "with maximal 32 EEW)", [FeatureStdExtZicsr, FeatureStdExtZvl32b]>; + def FeatureStdExtZve32f : RISCVExtension<"zve32f", 1, 0, "'Zve32f' (Vector Extensions for Embedded Processors " @@ -653,7 +691,8 @@ def FeatureStdExtZve64d def FeatureStdExtV : RISCVExtension<"v", 1, 0, "'V' (Vector Extension for Application Processors)", - [FeatureStdExtZvl128b, FeatureStdExtZve64d]>; + [FeatureStdExtZvl128b, FeatureStdExtZve64d]>, + RISCVExtensionBitmask<0, 21>; def FeatureStdExtZvfbfmin : RISCVExtension<"zvfbfmin", 1, 0, "'Zvbfmin' (Vector BF16 Converts)", @@ -673,12 +712,14 @@ def HasStdExtZvfbfwma : Predicate<"Subtarget->hasStdExtZvfbfwma()">, def FeatureStdExtZvfhmin : RISCVExtension<"zvfhmin", 1, 0, "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)", - [FeatureStdExtZve32f]>; + [FeatureStdExtZve32f]>, + RISCVExtensionBitmask<0, 51>; def FeatureStdExtZvfh : RISCVExtension<"zvfh", 1, 0, "'Zvfh' (Vector Half-Precision Floating-Point)", - [FeatureStdExtZvfhmin, FeatureStdExtZfhmin]>; + [FeatureStdExtZvfhmin, FeatureStdExtZfhmin]>, + RISCVExtensionBitmask<0, 50>; def HasStdExtZfhOrZvfh : Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZvfh()">, @@ -690,7 +731,8 @@ def HasStdExtZfhOrZvfh def FeatureStdExtZvkb : RISCVExtension<"zvkb", 1, 0, - "'Zvkb' (Vector Bit-manipulation used in Cryptography)">; + "'Zvkb' (Vector Bit-manipulation used in Cryptography)">, + RISCVExtensionBitmask<0, 52>; def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">, AssemblerPredicate<(all_of FeatureStdExtZvkb), "'Zvkb' (Vector Bit-manipulation used in Cryptography)">; @@ -698,35 +740,40 @@ def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">, def FeatureStdExtZvbb : RISCVExtension<"zvbb", 1, 0, "'Zvbb' (Vector basic bit-manipulation instructions)", - [FeatureStdExtZvkb]>; + [FeatureStdExtZvkb]>, + RISCVExtensionBitmask<0, 48>; def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">, AssemblerPredicate<(all_of FeatureStdExtZvbb), "'Zvbb' (Vector basic bit-manipulation instructions)">; def FeatureStdExtZvbc : RISCVExtension<"zvbc", 1, 0, - "'Zvbc' (Vector Carryless Multiplication)">; + "'Zvbc' (Vector Carryless Multiplication)">, + RISCVExtensionBitmask<0, 49>; def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">, AssemblerPredicate<(all_of FeatureStdExtZvbc), "'Zvbc' (Vector Carryless Multiplication)">; def FeatureStdExtZvkg : RISCVExtension<"zvkg", 1, 0, - "'Zvkg' (Vector GCM instructions for Cryptography)">; + "'Zvkg' (Vector GCM instructions for Cryptography)">, + RISCVExtensionBitmask<0, 53>; def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">, AssemblerPredicate<(all_of FeatureStdExtZvkg), "'Zvkg' (Vector GCM instructions for Cryptography)">; def FeatureStdExtZvkned : RISCVExtension<"zvkned", 1, 0, - "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">; + "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">, + RISCVExtensionBitmask<0, 54>; def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">, AssemblerPredicate<(all_of FeatureStdExtZvkned), "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">; def FeatureStdExtZvknha : RISCVExtension<"zvknha", 1, 0, - "'Zvknha' (Vector SHA-2 (SHA-256 only))">; + "'Zvknha' (Vector SHA-2 (SHA-256 only))">, + RISCVExtensionBitmask<0, 55>; def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">, AssemblerPredicate<(all_of FeatureStdExtZvknha), "'Zvknha' (Vector SHA-2 (SHA-256 only))">; @@ -734,7 +781,8 @@ def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">, def FeatureStdExtZvknhb : RISCVExtension<"zvknhb", 1, 0, "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))", - [FeatureStdExtZve64x]>; + [FeatureStdExtZve64x]>, + RISCVExtensionBitmask<0, 56>; def HasStdExtZvknhb : Predicate<"Subtarget->hasStdExtZvknhb()">, AssemblerPredicate<(all_of FeatureStdExtZvknhb), "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))">; @@ -745,21 +793,24 @@ def HasStdExtZvknhaOrZvknhb : Predicate<"Subtarget->hasStdExtZvknha() || Subtarg def FeatureStdExtZvksed : RISCVExtension<"zvksed", 1, 0, - "'Zvksed' (SM4 Block Cipher Instructions)">; + "'Zvksed' (SM4 Block Cipher Instructions)">, + RISCVExtensionBitmask<0, 57>; def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">, AssemblerPredicate<(all_of FeatureStdExtZvksed), "'Zvksed' (SM4 Block Cipher Instructions)">; def FeatureStdExtZvksh : RISCVExtension<"zvksh", 1, 0, - "'Zvksh' (SM3 Hash Function Instructions)">; + "'Zvksh' (SM3 Hash Function Instructions)">, + RISCVExtensionBitmask<0, 58>; def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">, AssemblerPredicate<(all_of FeatureStdExtZvksh), "'Zvksh' (SM3 Hash Function Instructions)">; def FeatureStdExtZvkt : RISCVExtension<"zvkt", 1, 0, - "'Zvkt' (Vector Data-Independent Execution Latency)">; + "'Zvkt' (Vector Data-Independent Execution Latency)">, + RISCVExtensionBitmask<0, 59>; // Zvk short-hand extensions @@ -796,7 +847,6 @@ def FeatureStdExtZvksg : RISCVExtension<"zvksg", 1, 0, "'Zvksg' (shorthand for 'Zvks' and 'Zvkg')", [FeatureStdExtZvks, FeatureStdExtZvkg]>; - // Vector instruction predicates def HasVInstructions : Predicate<"Subtarget->hasVInstructions()">, diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp index db1b5f689d7da..e2d12293e1cd2 100644 --- a/llvm/lib/TargetParser/RISCVTargetParser.cpp +++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp @@ -128,6 +128,33 @@ void getFeaturesForCPU(StringRef CPU, else EnabledFeatures.push_back(F.substr(1)); } + +namespace RISCVExtensionBitmaskTable { +#define GET_RISCVExtensionBitmaskTable_IMPL +#include "llvm/TargetParser/RISCVTargetParserDef.inc" + +} // namespace RISCVExtensionBitmaskTable + +namespace { +struct LessExtName { + bool operator()(const RISCVExtensionBitmaskTable::RISCVExtensionBitmask &LHS, + StringRef RHS) { + return StringRef(LHS.Name) < RHS; + } +}; +} // namespace + +static RISCVExtensionBitmaskTable::RISCVExtensionBitmask +getExtensionBitmask(StringRef ExtName) { + ArrayRef ExtBitmasks = + RISCVExtensionBitmaskTable::ExtensionBitmask; + auto *I = llvm::lower_bound(ExtBitmasks, ExtName, LessExtName()); + + if (I != ExtBitmasks.end() && ExtName.equals_insensitive(I->Name)) + return *I; + + return RISCVExtensionBitmaskTable::RISCVExtensionBitmask(); +} } // namespace RISCV namespace RISCVVType { diff --git a/llvm/test/TableGen/riscv-target-def.td b/llvm/test/TableGen/riscv-target-def.td index 7137cf96fd3d4..c071cfd731cb5 100644 --- a/llvm/test/TableGen/riscv-target-def.td +++ b/llvm/test/TableGen/riscv-target-def.td @@ -12,6 +12,11 @@ class RISCVExtension groupID, int bitPos> { + int GroupID = groupID; + int BitPos = bitPos; +} + class RISCVExperimentalExtension implies = [], string fieldname = !subst("Feature", "Has", NAME), @@ -23,7 +28,8 @@ class RISCVExperimentalExtension; + "'I' (Base Integer Instruction Set)">, + RISCVExtensionBitmask<0, 8>; def FeatureStdExtZicsr : RISCVExtension<"zicsr", 2, 0, @@ -36,7 +42,8 @@ def FeatureStdExtZifencei def FeatureStdExtF : RISCVExtension<"f", 2, 2, "'F' (Single-Precision Floating-Point)", - [FeatureStdExtZicsr]>; + [FeatureStdExtZicsr]>, + RISCVExtensionBitmask<0, 5>; def FeatureStdExtZidummy : RISCVExperimentalExtension<"zidummy", 0, 1, @@ -171,3 +178,10 @@ def ROCKET : RISCVTuneProcessorModel<"rocket", // CHECK-NEXT: TUNE_PROC(ROCKET, "rocket") // CHECK: #undef TUNE_PROC + +// CHECK: #ifdef GET_RISCVExtensionBitmaskTable_IMPL +// CHECK-NEXT: static const RISCVExtensionBitmask ExtensionBitmask[]={ +// CHECK-NEXT: {"f", 0, 5ULL}, +// CHECK-NEXT: {"i", 0, 8ULL}, +// CHECK-NEXT: }; +// CHECK-NEXT: #endif diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp index 04e9e0fa48db0..910488a14b985 100644 --- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp +++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp @@ -11,6 +11,7 @@ // //===----------------------------------------------------------------------===// +#include "llvm/ADT/DenseSet.h" #include "llvm/Support/RISCVISAUtils.h" #include "llvm/TableGen/Record.h" #include "llvm/TableGen/TableGenBackend.h" @@ -209,10 +210,46 @@ static void emitRISCVProcs(RecordKeeper &RK, raw_ostream &OS) { OS << "\n#undef TUNE_PROC\n"; } +static void emitRISCVExtensionBitmask(RecordKeeper &RK, raw_ostream &OS) { + + std::vector Extensions = + RK.getAllDerivedDefinitionsIfDefined("RISCVExtensionBitmask"); + llvm::sort(Extensions, [](const Record *Rec1, const Record *Rec2) { + return getExtensionName(Rec1) < getExtensionName(Rec2); + }); + +#ifndef NDEBUG + llvm::DenseSet> Seen; +#endif + + OS << "#ifdef GET_RISCVExtensionBitmaskTable_IMPL\n"; + OS << "static const RISCVExtensionBitmask ExtensionBitmask[]={\n"; + for (const Record *Rec : Extensions) { + unsigned GroupIDVal = Rec->getValueAsInt("GroupID"); + unsigned BitPosVal = Rec->getValueAsInt("BitPos"); + + StringRef ExtName = Rec->getValueAsString("Name"); + ExtName.consume_front("experimental-"); + +#ifndef NDEBUG + assert(Seen.insert(std::make_pair(GroupIDVal, BitPosVal)).second && + "duplicated bitmask"); +#endif + + OS << " {" + << "\"" << ExtName << "\"" + << ", " << GroupIDVal << ", " << BitPosVal << "ULL" + << "},\n"; + } + OS << "};\n"; + OS << "#endif\n"; +} + static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) { emitRISCVExtensions(RK, OS); emitRISCVProfiles(RK, OS); emitRISCVProcs(RK, OS); + emitRISCVExtensionBitmask(RK, OS); } static TableGen::Emitter::Opt X("gen-riscv-target-def", EmitRISCVTargetDef,