From ff3f2496f3f5bf8b0356c95467605e3e80cc35b0 Mon Sep 17 00:00:00 2001 From: Changpeng Fang Date: Wed, 3 Apr 2024 11:20:10 -0700 Subject: [PATCH] AMDGPU: Use PseudoInstr to name SIMCInstr for DSDIR and SOPs --- llvm/lib/Target/AMDGPU/DSDIRInstructions.td | 2 +- llvm/lib/Target/AMDGPU/SOPInstructions.td | 78 ++++++++++----------- 2 files changed, 40 insertions(+), 40 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/DSDIRInstructions.td b/llvm/lib/Target/AMDGPU/DSDIRInstructions.td index f4f02d2cebfd9..0541f0f656327 100644 --- a/llvm/lib/Target/AMDGPU/DSDIRInstructions.td +++ b/llvm/lib/Target/AMDGPU/DSDIRInstructions.td @@ -112,7 +112,7 @@ class DSDIR_Real : lds.Mnemonic # asm, ins, lds.is_direct>, - SIMCInstr { + SIMCInstr { let isPseudo = 0; let isCodeGenOnly = 0; diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td index d34ee34e5bbff..0b7d45ee8c027 100644 --- a/llvm/lib/Target/AMDGPU/SOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td @@ -1972,7 +1972,7 @@ class Select_gfx6_gfx7 : SIMCInstr { multiclass SOP1_Real_gfx11 op, string name = !tolower(NAME)> { defvar ps = !cast(NAME); def _gfx11 : SOP1_Real, - Select_gfx11; + Select_gfx11; if !ne(ps.Mnemonic, name) then def : MnemonicAlias, Requires<[isGFX11Only]>; } @@ -1980,14 +1980,14 @@ multiclass SOP1_Real_gfx11 op, string name = !tolower(NAME)> { multiclass SOP1_Real_gfx12 op, string name = !tolower(NAME)> { defvar ps = !cast(NAME); def _gfx12 : SOP1_Real, - Select_gfx12; + Select_gfx12; if !ne(ps.Mnemonic, name) then def : MnemonicAlias, Requires<[isGFX12Plus]>; } multiclass SOP1_M0_Real_gfx12 op> { def _gfx12 : SOP1_Real(NAME)>, - Select_gfx12(NAME).Mnemonic> { + Select_gfx12(NAME).PseudoInstr> { let Inst{7-0} = M0_gfx11plus.HWEncoding{7-0}; // Set Src0 encoding to M0 } } @@ -1995,7 +1995,7 @@ multiclass SOP1_M0_Real_gfx12 op> { multiclass SOP1_IMM_Real_gfx12 op> { defvar ps = !cast(NAME); def _gfx12 : SOP1_Real, - Select_gfx12; + Select_gfx12; } multiclass SOP1_Real_gfx11_gfx12 op, string name = !tolower(NAME)> : @@ -2106,7 +2106,7 @@ defm S_RNDNE_F16 : SOP1_Real_gfx11_gfx12<0x06e>; multiclass SOP1_Real_gfx10 op> { defvar ps = !cast(NAME); def _gfx10 : SOP1_Real, - Select_gfx10; + Select_gfx10; } multiclass SOP1_Real_gfx10_gfx11_gfx12 op> : @@ -2139,7 +2139,7 @@ defm S_MOVRELSD_2_B32 : SOP1_Real_gfx10<0x049>; multiclass SOP1_Real_gfx6_gfx7 op> { defvar ps = !cast(NAME); def _gfx6_gfx7 : SOP1_Real, - Select_gfx6_gfx7; + Select_gfx6_gfx7; } multiclass SOP1_Real_gfx6_gfx7_gfx10 op> : @@ -2205,7 +2205,7 @@ defm S_ABS_I32 : SOP1_Real_gfx6_gfx7_gfx10<0x034>; multiclass SOP2_Real_gfx12 op, string name = !tolower(NAME)> { defvar ps = !cast(NAME); def _gfx12 : SOP2_Real32, - Select_gfx12; + Select_gfx12; if !ne(ps.Mnemonic, name) then def : MnemonicAlias, Requires<[isGFX12Plus]>; } @@ -2222,7 +2222,7 @@ defm S_MAXIMUM_F16 : SOP2_Real_gfx12<0x052>; multiclass SOP2_Real_gfx11 op, string name = !tolower(NAME)> { defvar ps = !cast(NAME); def _gfx11 : SOP2_Real32, - Select_gfx11; + Select_gfx11; if !ne(ps.Mnemonic, name) then def : MnemonicAlias, Requires<[isGFX11Only]>; } @@ -2283,12 +2283,12 @@ defm S_MUL_U64 : SOP2_Real_gfx12<0x055>; multiclass SOP2_Real_FMAK_gfx12 op> { def _gfx12 : SOP2_Real64(NAME)>, - Select_gfx12(NAME).Mnemonic>; + Select_gfx12(NAME).PseudoInstr>; } multiclass SOP2_Real_FMAK_gfx11 op> { def _gfx11 : SOP2_Real64(NAME)>, - Select_gfx11(NAME).Mnemonic>; + Select_gfx11(NAME).PseudoInstr>; } multiclass SOP2_Real_FMAK_gfx11_gfx12 op> : @@ -2325,7 +2325,7 @@ defm S_MAX_F16 : SOP2_Real_gfx11_Renamed_gfx12<0x04c, "s_max_num_f16">; multiclass SOP2_Real_gfx10 op> { defvar ps = !cast(NAME); def _gfx10 : SOP2_Real32, - Select_gfx10; + Select_gfx10; } multiclass SOP2_Real_gfx10_gfx11_gfx12 op> : @@ -2348,7 +2348,7 @@ defm S_MUL_HI_I32 : SOP2_Real_gfx10<0x036>; multiclass SOP2_Real_gfx6_gfx7 op> { defvar ps = !cast(NAME); def _gfx6_gfx7 : SOP2_Real32, - Select_gfx6_gfx7; + Select_gfx6_gfx7; } multiclass SOP2_Real_gfx6_gfx7_gfx10 op> : @@ -2410,24 +2410,24 @@ defm S_ABSDIFF_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x02c>; multiclass SOPK_Real32_gfx12 op, string name = !tolower(NAME)> { defvar ps = !cast(NAME); def _gfx12 : SOPK_Real32, - Select_gfx12; + Select_gfx12; if !ne(ps.Mnemonic, name) then def : MnemonicAlias, Requires<[isGFX12Plus]>; } multiclass SOPK_Real32_gfx11 op> { def _gfx11 : SOPK_Real32(NAME)>, - Select_gfx11(NAME).Mnemonic>; + Select_gfx11(NAME).PseudoInstr>; } multiclass SOPK_Real64_gfx12 op> { def _gfx12 : SOPK_Real64(NAME)>, - Select_gfx12(NAME).Mnemonic>; + Select_gfx12(NAME).PseudoInstr>; } multiclass SOPK_Real64_gfx11 op> { def _gfx11 : SOPK_Real64(NAME)>, - Select_gfx11(NAME).Mnemonic>; + Select_gfx11(NAME).PseudoInstr>; } multiclass SOPK_Real32_gfx11_gfx12 op> : @@ -2454,13 +2454,13 @@ defm S_WAITCNT_LGKMCNT : SOPK_Real32_gfx11<0x01b>; multiclass SOPK_Real32_gfx10 op> { defvar ps = !cast(NAME); def _gfx10 : SOPK_Real32, - Select_gfx10; + Select_gfx10; } multiclass SOPK_Real64_gfx10 op> { defvar ps = !cast(NAME); def _gfx10 : SOPK_Real64, - Select_gfx10; + Select_gfx10; } multiclass SOPK_Real32_gfx10_gfx11 op> : @@ -2485,13 +2485,13 @@ defm S_SUBVECTOR_LOOP_END : SOPK_Real32_gfx10<0x01c>; multiclass SOPK_Real32_gfx6_gfx7 op> { defvar ps = !cast(NAME); def _gfx6_gfx7 : SOPK_Real32, - Select_gfx6_gfx7; + Select_gfx6_gfx7; } multiclass SOPK_Real64_gfx6_gfx7 op> { defvar ps = !cast(NAME); def _gfx6_gfx7 : SOPK_Real64, - Select_gfx6_gfx7; + Select_gfx6_gfx7; } multiclass SOPK_Real32_gfx6_gfx7_gfx10 op> : @@ -2539,7 +2539,7 @@ defm S_SETREG_IMM32_B32 : SOPK_Real64_gfx6_gfx7_gfx10<0x015>; multiclass SOPP_Real_32_gfx12 op, string name = !tolower(NAME)> { defvar ps = !cast(NAME); def _gfx12 : SOPP_Real_32, - Select_gfx12; + Select_gfx12; if !ne(ps.Mnemonic, name) then def : MnemonicAlias, Requires<[isGFX12Plus]>; } @@ -2564,7 +2564,7 @@ defm S_WAIT_STORECNT_DSCNT : SOPP_Real_32_gfx12<0x049>; multiclass SOPP_Real_32_gfx11 op, string name = !tolower(NAME)> { defvar ps = !cast(NAME); def _gfx11 : SOPP_Real_32, - Select_gfx11, + Select_gfx11, SOPPRelaxTable<0, ps.KeyName, "_gfx11">; if !ne(ps.Mnemonic, name) then def : MnemonicAlias, Requires<[isGFX11Only]>; @@ -2572,13 +2572,13 @@ multiclass SOPP_Real_32_gfx11 op, string name = !tolower(NAME)> { multiclass SOPP_Real_64_gfx12 op> { def _gfx12 : SOPP_Real_64(NAME), !cast(NAME).Mnemonic>, - Select_gfx12(NAME).Mnemonic>, + Select_gfx12(NAME).PseudoInstr>, SOPPRelaxTable<1, !cast(NAME).KeyName, "_gfx12">; } multiclass SOPP_Real_64_gfx11 op> { def _gfx11 : SOPP_Real_64(NAME), !cast(NAME).Mnemonic>, - Select_gfx11(NAME).Mnemonic>, + Select_gfx11(NAME).PseudoInstr>, SOPPRelaxTable<1, !cast(NAME).KeyName, "_gfx11">; } @@ -2654,21 +2654,21 @@ defm S_SINGLEUSE_VDST : SOPP_Real_32_gfx11_gfx12<0x013>; multiclass SOPP_Real_32_gfx6_gfx7 op> { defvar ps = !cast(NAME); def _gfx6_gfx7 : SOPP_Real_32(NAME).Mnemonic>, - Select_gfx6_gfx7, + Select_gfx6_gfx7, SOPPRelaxTable<0, ps.KeyName, "_gfx6_gfx7">; } multiclass SOPP_Real_32_gfx8_gfx9 op> { defvar ps = !cast(NAME); def _vi : SOPP_Real_32, - Select_vi, + Select_vi, SOPPRelaxTable<0, ps.KeyName, "_vi">; } multiclass SOPP_Real_32_gfx10 op> { defvar ps = !cast(NAME); def _gfx10 : SOPP_Real_32, - Select_gfx10, + Select_gfx10, SOPPRelaxTable<0, ps.KeyName, "_gfx10">; } @@ -2691,21 +2691,21 @@ multiclass SOPP_Real_32_gfx10_gfx11_gfx12 op> : multiclass SOPP_Real_64_gfx6_gfx7 op> { defvar ps = !cast(NAME); def _gfx6_gfx7 : SOPP_Real_64, - Select_gfx6_gfx7, + Select_gfx6_gfx7, SOPPRelaxTable<1, ps.KeyName, "_gfx6_gfx7">; } multiclass SOPP_Real_64_gfx8_gfx9 op> { defvar ps = !cast(NAME); def _vi : SOPP_Real_64, - Select_vi, + Select_vi, SOPPRelaxTable<1, ps.KeyName, "_vi">; } multiclass SOPP_Real_64_gfx10 op> { defvar ps = !cast(NAME); def _gfx10 : SOPP_Real_64, - Select_gfx10, + Select_gfx10, SOPPRelaxTable<1, ps.KeyName, "_gfx10">; } @@ -2771,12 +2771,12 @@ defm S_CBRANCH_CDBGSYS_AND_USER : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_ multiclass SOPC_Real_gfx12 op> { def _gfx12 : SOPC_Real(NAME)>, - Select_gfx12(NAME).Mnemonic>; + Select_gfx12(NAME).PseudoInstr>; } multiclass SOPC_Real_gfx11 op> { def _gfx11 : SOPC_Real(NAME)>, - Select_gfx11(NAME).Mnemonic>; + Select_gfx11(NAME).PseudoInstr>; } multiclass SOPC_Real_gfx11_gfx12 op> : @@ -2826,19 +2826,19 @@ defm S_CMP_NLT_F16 : SOPC_Real_gfx11_gfx12<0x5e>; multiclass SOPC_Real_gfx6_gfx7 op> { defvar ps = !cast(NAME); def _gfx6_gfx7 : SOPC_Real, - Select_gfx6_gfx7; + Select_gfx6_gfx7; } multiclass SOPC_Real_gfx8_gfx9 op> { defvar ps = !cast(NAME); def _vi : SOPC_Real, - Select_vi; + Select_vi; } multiclass SOPC_Real_gfx10 op> { defvar ps = !cast(NAME); def _gfx10 : SOPC_Real, - Select_gfx10; + Select_gfx10; } multiclass SOPC_Real_gfx8_gfx9_gfx10 op> : @@ -2878,15 +2878,15 @@ defm S_CMP_LG_U64 : SOPC_Real_gfx8_gfx9_gfx10<0x13>; class SOP1_Real_vi op, SOP1_Pseudo ps> : SOP1_Real, - Select_vi; + Select_vi; class SOP2_Real_vi op, SOP2_Pseudo ps> : SOP2_Real32, - Select_vi; + Select_vi; class SOPK_Real_vi op, SOPK_Pseudo ps> : SOPK_Real32, - Select_vi; + Select_vi; def S_MOV_B32_vi : SOP1_Real_vi <0x00, S_MOV_B32>; def S_MOV_B64_vi : SOP1_Real_vi <0x01, S_MOV_B64>; @@ -3007,7 +3007,7 @@ def S_GETREG_B32_vi : SOPK_Real_vi <0x11, S_GETREG_B32>; def S_SETREG_B32_vi : SOPK_Real_vi <0x12, S_SETREG_B32>; //def S_GETREG_REGRD_B32_vi : SOPK_Real_vi <0x13, S_GETREG_REGRD_B32>; // see pseudo for comments def S_SETREG_IMM32_B32_vi : SOPK_Real64<0x14, S_SETREG_IMM32_B32>, - Select_vi; + Select_vi; def S_CALL_B64_vi : SOPK_Real_vi <0x15, S_CALL_B64>;