diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index 18d51087ff5fb..cb4eddfe5320f 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -8168,20 +8168,6 @@ void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst, bool IsAtomicReturn = false; if (IsAtomic) { - for (unsigned i = FirstOperandIdx, e = Operands.size(); i != e; ++i) { - AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]); - if (!Op.isCPol()) - continue; - IsAtomicReturn = Op.getImm() & AMDGPU::CPol::GLC; - break; - } - - if (!IsAtomicReturn) { - int NewOpc = AMDGPU::getAtomicNoRetOp(Inst.getOpcode()); - if (NewOpc != -1) - Inst.setOpcode(NewOpc); - } - IsAtomicReturn = MII.get(Inst.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet; } diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td index 0636a74a61dc5..7bb92256fbddd 100644 --- a/llvm/lib/Target/AMDGPU/BUFInstructions.td +++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td @@ -747,8 +747,7 @@ class MUBUF_AtomicNoRet_Pseudo.ret, getMUBUFAsmOps.ret, - pattern>, - AtomicNoRet.ret, 0> { + pattern> { let PseudoInstr = opName # "_" # getAddrName.ret; let glc_value = 0; let dlc_value = 0; @@ -768,8 +767,7 @@ class MUBUF_AtomicRet_Pseudo.ret, getMUBUFAsmOps.ret, - pattern>, - AtomicNoRet.ret, 1> { + pattern> { let PseudoInstr = opName # "_rtn_" # getAddrName.ret; let glc_value = 1; let dlc_value = 0; @@ -2511,34 +2509,26 @@ multiclass MUBUF_Real_Atomic_gfx11_Renamed_impl op, bit is_return, string real_name> { defvar Rtn = !if(is_return, "_RTN", ""); def _BOTHEN#Rtn#_gfx11 : - MUBUF_Real_Atomic_gfx11_impl, - AtomicNoRet; + MUBUF_Real_Atomic_gfx11_impl; def _IDXEN#Rtn#_gfx11 : - MUBUF_Real_Atomic_gfx11_impl, - AtomicNoRet; + MUBUF_Real_Atomic_gfx11_impl; def _OFFEN#Rtn#_gfx11 : - MUBUF_Real_Atomic_gfx11_impl, - AtomicNoRet; + MUBUF_Real_Atomic_gfx11_impl; def _OFFSET#Rtn#_gfx11 : - MUBUF_Real_Atomic_gfx11_impl, - AtomicNoRet; + MUBUF_Real_Atomic_gfx11_impl; } multiclass MUBUF_Real_Atomic_gfx12_Renamed_impl op, bit is_return, string real_name> { defvar Rtn = !if(is_return, "_RTN", ""); def _BOTHEN#Rtn#_gfx12 : - MUBUF_Real_Atomic_gfx12_impl, - AtomicNoRet; + MUBUF_Real_Atomic_gfx12_impl; def _IDXEN#Rtn#_gfx12 : - MUBUF_Real_Atomic_gfx12_impl, - AtomicNoRet; + MUBUF_Real_Atomic_gfx12_impl; def _OFFEN#Rtn#_gfx12 : - MUBUF_Real_Atomic_gfx12_impl, - AtomicNoRet; + MUBUF_Real_Atomic_gfx12_impl; def _OFFSET#Rtn#_gfx12 : - MUBUF_Real_Atomic_gfx12_impl, - AtomicNoRet; + MUBUF_Real_Atomic_gfx12_impl; } multiclass MUBUF_Real_Atomic_gfx11_gfx12_Renamed_impl op, bit is_return, @@ -2695,32 +2685,24 @@ multiclass MUBUF_Real_AllAddr_Lds_gfx10 op, bit isTFE = 0> { } multiclass MUBUF_Real_Atomics_RTN_gfx10 op> { def _BOTHEN_RTN_gfx10 : - MUBUF_Real_gfx10(NAME#"_BOTHEN_RTN")>, - AtomicNoRet; + MUBUF_Real_gfx10(NAME#"_BOTHEN_RTN")>; def _IDXEN_RTN_gfx10 : - MUBUF_Real_gfx10(NAME#"_IDXEN_RTN")>, - AtomicNoRet; + MUBUF_Real_gfx10(NAME#"_IDXEN_RTN")>; def _OFFEN_RTN_gfx10 : - MUBUF_Real_gfx10(NAME#"_OFFEN_RTN")>, - AtomicNoRet; + MUBUF_Real_gfx10(NAME#"_OFFEN_RTN")>; def _OFFSET_RTN_gfx10 : - MUBUF_Real_gfx10(NAME#"_OFFSET_RTN")>, - AtomicNoRet; + MUBUF_Real_gfx10(NAME#"_OFFSET_RTN")>; } multiclass MUBUF_Real_Atomics_gfx10 op> : MUBUF_Real_Atomics_RTN_gfx10 { def _BOTHEN_gfx10 : - MUBUF_Real_gfx10(NAME#"_BOTHEN")>, - AtomicNoRet; + MUBUF_Real_gfx10(NAME#"_BOTHEN")>; def _IDXEN_gfx10 : - MUBUF_Real_gfx10(NAME#"_IDXEN")>, - AtomicNoRet; + MUBUF_Real_gfx10(NAME#"_IDXEN")>; def _OFFEN_gfx10 : - MUBUF_Real_gfx10(NAME#"_OFFEN")>, - AtomicNoRet; + MUBUF_Real_gfx10(NAME#"_OFFEN")>; def _OFFSET_gfx10 : - MUBUF_Real_gfx10(NAME#"_OFFSET")>, - AtomicNoRet; + MUBUF_Real_gfx10(NAME#"_OFFSET")>; } defm BUFFER_STORE_BYTE_D16_HI : MUBUF_Real_AllAddr_gfx10<0x019>; @@ -2795,36 +2777,26 @@ multiclass MUBUF_Real_AllAddr_Lds_gfx6_gfx7 op, bit isTFE = 0> { } multiclass MUBUF_Real_Atomics_gfx6_gfx7 op> { def _ADDR64_gfx6_gfx7 : - MUBUF_Real_gfx6_gfx7(NAME#"_ADDR64")>, - AtomicNoRet; + MUBUF_Real_gfx6_gfx7(NAME#"_ADDR64")>; def _BOTHEN_gfx6_gfx7 : - MUBUF_Real_gfx6_gfx7(NAME#"_BOTHEN")>, - AtomicNoRet; + MUBUF_Real_gfx6_gfx7(NAME#"_BOTHEN")>; def _IDXEN_gfx6_gfx7 : - MUBUF_Real_gfx6_gfx7(NAME#"_IDXEN")>, - AtomicNoRet; + MUBUF_Real_gfx6_gfx7(NAME#"_IDXEN")>; def _OFFEN_gfx6_gfx7 : - MUBUF_Real_gfx6_gfx7(NAME#"_OFFEN")>, - AtomicNoRet; + MUBUF_Real_gfx6_gfx7(NAME#"_OFFEN")>; def _OFFSET_gfx6_gfx7 : - MUBUF_Real_gfx6_gfx7(NAME#"_OFFSET")>, - AtomicNoRet; + MUBUF_Real_gfx6_gfx7(NAME#"_OFFSET")>; def _ADDR64_RTN_gfx6_gfx7 : - MUBUF_Real_gfx6_gfx7(NAME#"_ADDR64_RTN")>, - AtomicNoRet; + MUBUF_Real_gfx6_gfx7(NAME#"_ADDR64_RTN")>; def _BOTHEN_RTN_gfx6_gfx7 : - MUBUF_Real_gfx6_gfx7(NAME#"_BOTHEN_RTN")>, - AtomicNoRet; + MUBUF_Real_gfx6_gfx7(NAME#"_BOTHEN_RTN")>; def _IDXEN_RTN_gfx6_gfx7 : - MUBUF_Real_gfx6_gfx7(NAME#"_IDXEN_RTN")>, - AtomicNoRet; + MUBUF_Real_gfx6_gfx7(NAME#"_IDXEN_RTN")>; def _OFFEN_RTN_gfx6_gfx7 : - MUBUF_Real_gfx6_gfx7(NAME#"_OFFEN_RTN")>, - AtomicNoRet; + MUBUF_Real_gfx6_gfx7(NAME#"_OFFEN_RTN")>; def _OFFSET_RTN_gfx6_gfx7 : - MUBUF_Real_gfx6_gfx7(NAME#"_OFFSET_RTN")>, - AtomicNoRet; + MUBUF_Real_gfx6_gfx7(NAME#"_OFFSET_RTN")>; } multiclass MUBUF_Real_AllAddr_gfx6_gfx7_gfx10 op> : @@ -3081,9 +3053,7 @@ class MUBUF_Real_Base_vi op, MUBUF_Pseudo ps, int Enc, bit has_sccb = ps.has_sccb> : MUBUF_Real, Enc64, - SIMCInstr, - AtomicNoRet { + SIMCInstr { let Inst{11-0} = !if(ps.has_offset, offset, ?); let Inst{12} = ps.offen; diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td index 7d79b9bba243c..219ff37b0a15c 100644 --- a/llvm/lib/Target/AMDGPU/DSInstructions.td +++ b/llvm/lib/Target/AMDGPU/DSInstructions.td @@ -116,19 +116,16 @@ class DS_1A1D_NORET } multiclass DS_1A1D_NORET_mc { - def "" : DS_1A1D_NORET, - AtomicNoRet; + def "" : DS_1A1D_NORET; let has_m0_read = 0 in { - def _gfx9 : DS_1A1D_NORET, - AtomicNoRet; + def _gfx9 : DS_1A1D_NORET; } } multiclass DS_1A1D_NORET_mc_gfx9 { let has_m0_read = 0 in { - def "" : DS_1A1D_NORET, - AtomicNoRet; + def "" : DS_1A1D_NORET; } } @@ -144,12 +141,10 @@ class DS_1A2D_NORET { - def "" : DS_1A2D_NORET, - AtomicNoRet; + def "" : DS_1A2D_NORET; let has_m0_read = 0 in { - def _gfx9 : DS_1A2D_NORET, - AtomicNoRet; + def _gfx9 : DS_1A2D_NORET; } } @@ -200,24 +195,17 @@ class DS_1A1D_RET { - def "" : DS_1A1D_RET, - AtomicNoRet; +multiclass DS_1A1D_RET_mc { + def "" : DS_1A1D_RET; let has_m0_read = 0 in { - def _gfx9 : DS_1A1D_RET, - AtomicNoRet; + def _gfx9 : DS_1A1D_RET; } } -multiclass DS_1A1D_RET_mc_gfx9 { +multiclass DS_1A1D_RET_mc_gfx9 { let has_m0_read = 0 in { - def "" : DS_1A1D_RET, - AtomicNoRet; + def "" : DS_1A1D_RET; } } @@ -237,14 +225,11 @@ class DS_1A2D_RET { - def "" : DS_1A2D_RET, - AtomicNoRet; + def "" : DS_1A2D_RET; let has_m0_read = 0 in { - def _gfx9 : DS_1A2D_RET, - AtomicNoRet; + def _gfx9 : DS_1A2D_RET; } } @@ -489,24 +474,24 @@ def DS_WRITE_ADDTID_B32 : DS_0A1D_NORET<"ds_write_addtid_b32">; let SubtargetPredicate = HasLdsAtomicAddF64 in { defm DS_ADD_F64 : DS_1A1D_NORET_mc_gfx9<"ds_add_f64", VReg_64>; - defm DS_ADD_RTN_F64 : DS_1A1D_RET_mc_gfx9<"ds_add_rtn_f64", VReg_64, "ds_add_f64">; + defm DS_ADD_RTN_F64 : DS_1A1D_RET_mc_gfx9<"ds_add_rtn_f64", VReg_64>; } // End SubtargetPredicate = HasLdsAtomicAddF64 let SubtargetPredicate = HasAtomicDsPkAdd16Insts in { defm DS_PK_ADD_F16 : DS_1A1D_NORET_mc<"ds_pk_add_f16">; - defm DS_PK_ADD_RTN_F16 : DS_1A1D_RET_mc<"ds_pk_add_rtn_f16", VGPR_32, "ds_pk_add_f16">; + defm DS_PK_ADD_RTN_F16 : DS_1A1D_RET_mc<"ds_pk_add_rtn_f16", VGPR_32>; defm DS_PK_ADD_BF16 : DS_1A1D_NORET_mc<"ds_pk_add_bf16">; - defm DS_PK_ADD_RTN_BF16 : DS_1A1D_RET_mc<"ds_pk_add_rtn_bf16", VGPR_32, "ds_pk_add_bf16">; + defm DS_PK_ADD_RTN_BF16 : DS_1A1D_RET_mc<"ds_pk_add_rtn_bf16", VGPR_32>; } // End SubtargetPredicate = HasAtomicDsPkAdd16Insts defm DS_CMPSTORE_B32 : DS_1A2D_NORET_mc<"ds_cmpstore_b32">; defm DS_CMPSTORE_F32 : DS_1A2D_NORET_mc<"ds_cmpstore_f32">; defm DS_CMPSTORE_B64 : DS_1A2D_NORET_mc<"ds_cmpstore_b64", VReg_64>; defm DS_CMPSTORE_F64 : DS_1A2D_NORET_mc<"ds_cmpstore_f64", VReg_64>; -defm DS_CMPSTORE_RTN_B32 : DS_1A2D_RET_mc<"ds_cmpstore_rtn_b32", VGPR_32, "ds_cmpstore_b32">; -defm DS_CMPSTORE_RTN_F32 : DS_1A2D_RET_mc<"ds_cmpstore_rtn_f32", VGPR_32, "ds_cmpstore_f32">; -defm DS_CMPSTORE_RTN_B64 : DS_1A2D_RET_mc<"ds_cmpstore_rtn_b64", VReg_64, "ds_cmpstore_b64">; -defm DS_CMPSTORE_RTN_F64 : DS_1A2D_RET_mc<"ds_cmpstore_rtn_f64", VReg_64, "ds_cmpstore_f64">; +defm DS_CMPSTORE_RTN_B32 : DS_1A2D_RET_mc<"ds_cmpstore_rtn_b32", VGPR_32>; +defm DS_CMPSTORE_RTN_F32 : DS_1A2D_RET_mc<"ds_cmpstore_rtn_f32", VGPR_32>; +defm DS_CMPSTORE_RTN_B64 : DS_1A2D_RET_mc<"ds_cmpstore_rtn_b64", VReg_64>; +defm DS_CMPSTORE_RTN_F64 : DS_1A2D_RET_mc<"ds_cmpstore_rtn_f64", VReg_64>; defm DS_MSKOR_B32 : DS_1A2D_NORET_mc<"ds_mskor_b32">; defm DS_CMPST_B32 : DS_1A2D_NORET_mc<"ds_cmpst_b32">; @@ -535,49 +520,49 @@ defm DS_CMPST_F64 : DS_1A2D_NORET_mc<"ds_cmpst_f64", VReg_64>; defm DS_MIN_F64 : DS_1A1D_NORET_mc<"ds_min_f64", VReg_64>; defm DS_MAX_F64 : DS_1A1D_NORET_mc<"ds_max_f64", VReg_64>; -defm DS_ADD_RTN_U32 : DS_1A1D_RET_mc<"ds_add_rtn_u32", VGPR_32, "ds_add_u32">; +defm DS_ADD_RTN_U32 : DS_1A1D_RET_mc<"ds_add_rtn_u32", VGPR_32>; let SubtargetPredicate = HasLDSFPAtomicAdd in { -defm DS_ADD_RTN_F32 : DS_1A1D_RET_mc<"ds_add_rtn_f32", VGPR_32, "ds_add_f32">; -} -defm DS_SUB_RTN_U32 : DS_1A1D_RET_mc<"ds_sub_rtn_u32", VGPR_32, "ds_sub_u32">; -defm DS_RSUB_RTN_U32 : DS_1A1D_RET_mc<"ds_rsub_rtn_u32", VGPR_32, "ds_rsub_u32">; -defm DS_INC_RTN_U32 : DS_1A1D_RET_mc<"ds_inc_rtn_u32", VGPR_32, "ds_inc_u32">; -defm DS_DEC_RTN_U32 : DS_1A1D_RET_mc<"ds_dec_rtn_u32", VGPR_32, "ds_dec_u32">; -defm DS_MIN_RTN_I32 : DS_1A1D_RET_mc<"ds_min_rtn_i32", VGPR_32, "ds_min_i32">; -defm DS_MAX_RTN_I32 : DS_1A1D_RET_mc<"ds_max_rtn_i32", VGPR_32, "ds_max_i32">; -defm DS_MIN_RTN_U32 : DS_1A1D_RET_mc<"ds_min_rtn_u32", VGPR_32, "ds_min_u32">; -defm DS_MAX_RTN_U32 : DS_1A1D_RET_mc<"ds_max_rtn_u32", VGPR_32, "ds_max_u32">; -defm DS_AND_RTN_B32 : DS_1A1D_RET_mc<"ds_and_rtn_b32", VGPR_32, "ds_and_b32">; -defm DS_OR_RTN_B32 : DS_1A1D_RET_mc<"ds_or_rtn_b32", VGPR_32, "ds_or_b32">; -defm DS_XOR_RTN_B32 : DS_1A1D_RET_mc<"ds_xor_rtn_b32", VGPR_32, "ds_xor_b32">; -defm DS_MSKOR_RTN_B32 : DS_1A2D_RET_mc<"ds_mskor_rtn_b32", VGPR_32, "ds_mskor_b32">; -defm DS_CMPST_RTN_B32 : DS_1A2D_RET_mc<"ds_cmpst_rtn_b32", VGPR_32, "ds_cmpst_b32">; -defm DS_CMPST_RTN_F32 : DS_1A2D_RET_mc<"ds_cmpst_rtn_f32", VGPR_32, "ds_cmpst_f32">; -defm DS_MIN_RTN_F32 : DS_1A1D_RET_mc<"ds_min_rtn_f32", VGPR_32, "ds_min_f32">; -defm DS_MAX_RTN_F32 : DS_1A1D_RET_mc<"ds_max_rtn_f32", VGPR_32, "ds_max_f32">; +defm DS_ADD_RTN_F32 : DS_1A1D_RET_mc<"ds_add_rtn_f32", VGPR_32>; +} +defm DS_SUB_RTN_U32 : DS_1A1D_RET_mc<"ds_sub_rtn_u32", VGPR_32>; +defm DS_RSUB_RTN_U32 : DS_1A1D_RET_mc<"ds_rsub_rtn_u32", VGPR_32>; +defm DS_INC_RTN_U32 : DS_1A1D_RET_mc<"ds_inc_rtn_u32", VGPR_32>; +defm DS_DEC_RTN_U32 : DS_1A1D_RET_mc<"ds_dec_rtn_u32", VGPR_32>; +defm DS_MIN_RTN_I32 : DS_1A1D_RET_mc<"ds_min_rtn_i32", VGPR_32>; +defm DS_MAX_RTN_I32 : DS_1A1D_RET_mc<"ds_max_rtn_i32", VGPR_32>; +defm DS_MIN_RTN_U32 : DS_1A1D_RET_mc<"ds_min_rtn_u32", VGPR_32>; +defm DS_MAX_RTN_U32 : DS_1A1D_RET_mc<"ds_max_rtn_u32", VGPR_32>; +defm DS_AND_RTN_B32 : DS_1A1D_RET_mc<"ds_and_rtn_b32", VGPR_32>; +defm DS_OR_RTN_B32 : DS_1A1D_RET_mc<"ds_or_rtn_b32", VGPR_32>; +defm DS_XOR_RTN_B32 : DS_1A1D_RET_mc<"ds_xor_rtn_b32", VGPR_32>; +defm DS_MSKOR_RTN_B32 : DS_1A2D_RET_mc<"ds_mskor_rtn_b32", VGPR_32>; +defm DS_CMPST_RTN_B32 : DS_1A2D_RET_mc<"ds_cmpst_rtn_b32", VGPR_32>; +defm DS_CMPST_RTN_F32 : DS_1A2D_RET_mc<"ds_cmpst_rtn_f32", VGPR_32>; +defm DS_MIN_RTN_F32 : DS_1A1D_RET_mc<"ds_min_rtn_f32", VGPR_32>; +defm DS_MAX_RTN_F32 : DS_1A1D_RET_mc<"ds_max_rtn_f32", VGPR_32>; defm DS_WRXCHG_RTN_B32 : DS_1A1D_RET_mc<"ds_wrxchg_rtn_b32">; defm DS_WRXCHG2_RTN_B32 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2_rtn_b32", VReg_64, VGPR_32>; defm DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2st64_rtn_b32", VReg_64, VGPR_32>; -defm DS_ADD_RTN_U64 : DS_1A1D_RET_mc<"ds_add_rtn_u64", VReg_64, "ds_add_u64">; -defm DS_SUB_RTN_U64 : DS_1A1D_RET_mc<"ds_sub_rtn_u64", VReg_64, "ds_sub_u64">; -defm DS_RSUB_RTN_U64 : DS_1A1D_RET_mc<"ds_rsub_rtn_u64", VReg_64, "ds_rsub_u64">; -defm DS_INC_RTN_U64 : DS_1A1D_RET_mc<"ds_inc_rtn_u64", VReg_64, "ds_inc_u64">; -defm DS_DEC_RTN_U64 : DS_1A1D_RET_mc<"ds_dec_rtn_u64", VReg_64, "ds_dec_u64">; -defm DS_MIN_RTN_I64 : DS_1A1D_RET_mc<"ds_min_rtn_i64", VReg_64, "ds_min_i64">; -defm DS_MAX_RTN_I64 : DS_1A1D_RET_mc<"ds_max_rtn_i64", VReg_64, "ds_max_i64">; -defm DS_MIN_RTN_U64 : DS_1A1D_RET_mc<"ds_min_rtn_u64", VReg_64, "ds_min_u64">; -defm DS_MAX_RTN_U64 : DS_1A1D_RET_mc<"ds_max_rtn_u64", VReg_64, "ds_max_u64">; -defm DS_AND_RTN_B64 : DS_1A1D_RET_mc<"ds_and_rtn_b64", VReg_64, "ds_and_b64">; -defm DS_OR_RTN_B64 : DS_1A1D_RET_mc<"ds_or_rtn_b64", VReg_64, "ds_or_b64">; -defm DS_XOR_RTN_B64 : DS_1A1D_RET_mc<"ds_xor_rtn_b64", VReg_64, "ds_xor_b64">; -defm DS_MSKOR_RTN_B64 : DS_1A2D_RET_mc<"ds_mskor_rtn_b64", VReg_64, "ds_mskor_b64">; -defm DS_CMPST_RTN_B64 : DS_1A2D_RET_mc<"ds_cmpst_rtn_b64", VReg_64, "ds_cmpst_b64">; -defm DS_CMPST_RTN_F64 : DS_1A2D_RET_mc<"ds_cmpst_rtn_f64", VReg_64, "ds_cmpst_f64">; -defm DS_MIN_RTN_F64 : DS_1A1D_RET_mc<"ds_min_rtn_f64", VReg_64, "ds_min_f64">; -defm DS_MAX_RTN_F64 : DS_1A1D_RET_mc<"ds_max_rtn_f64", VReg_64, "ds_max_f64">; +defm DS_ADD_RTN_U64 : DS_1A1D_RET_mc<"ds_add_rtn_u64", VReg_64>; +defm DS_SUB_RTN_U64 : DS_1A1D_RET_mc<"ds_sub_rtn_u64", VReg_64>; +defm DS_RSUB_RTN_U64 : DS_1A1D_RET_mc<"ds_rsub_rtn_u64", VReg_64>; +defm DS_INC_RTN_U64 : DS_1A1D_RET_mc<"ds_inc_rtn_u64", VReg_64>; +defm DS_DEC_RTN_U64 : DS_1A1D_RET_mc<"ds_dec_rtn_u64", VReg_64>; +defm DS_MIN_RTN_I64 : DS_1A1D_RET_mc<"ds_min_rtn_i64", VReg_64>; +defm DS_MAX_RTN_I64 : DS_1A1D_RET_mc<"ds_max_rtn_i64", VReg_64>; +defm DS_MIN_RTN_U64 : DS_1A1D_RET_mc<"ds_min_rtn_u64", VReg_64>; +defm DS_MAX_RTN_U64 : DS_1A1D_RET_mc<"ds_max_rtn_u64", VReg_64>; +defm DS_AND_RTN_B64 : DS_1A1D_RET_mc<"ds_and_rtn_b64", VReg_64>; +defm DS_OR_RTN_B64 : DS_1A1D_RET_mc<"ds_or_rtn_b64", VReg_64>; +defm DS_XOR_RTN_B64 : DS_1A1D_RET_mc<"ds_xor_rtn_b64", VReg_64>; +defm DS_MSKOR_RTN_B64 : DS_1A2D_RET_mc<"ds_mskor_rtn_b64", VReg_64>; +defm DS_CMPST_RTN_B64 : DS_1A2D_RET_mc<"ds_cmpst_rtn_b64", VReg_64>; +defm DS_CMPST_RTN_F64 : DS_1A2D_RET_mc<"ds_cmpst_rtn_f64", VReg_64>; +defm DS_MIN_RTN_F64 : DS_1A1D_RET_mc<"ds_min_rtn_f64", VReg_64>; +defm DS_MAX_RTN_F64 : DS_1A1D_RET_mc<"ds_max_rtn_f64", VReg_64>; defm DS_WRXCHG_RTN_B64 : DS_1A1D_RET_mc<"ds_wrxchg_rtn_b64", VReg_64>; defm DS_WRXCHG2_RTN_B64 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2_rtn_b64", VReg_128, VReg_64>; @@ -740,9 +725,9 @@ def DS_BVH_STACK_RTN_B32 : DS_BVH_STACK<"ds_bvh_stack_rtn_b32">; let SubtargetPredicate = isGFX12Plus in { defm DS_COND_SUB_U32 : DS_1A1D_NORET_mc<"ds_cond_sub_u32">; -defm DS_COND_SUB_RTN_U32 : DS_1A1D_RET_mc<"ds_cond_sub_rtn_u32", VGPR_32, "ds_cond_sub_u32">; +defm DS_COND_SUB_RTN_U32 : DS_1A1D_RET_mc<"ds_cond_sub_rtn_u32", VGPR_32>; defm DS_SUB_CLAMP_U32 : DS_1A1D_NORET_mc<"ds_sub_clamp_u32">; -defm DS_SUB_CLAMP_RTN_U32 : DS_1A1D_RET_mc<"ds_sub_clamp_rtn_u32", VGPR_32, "ds_sub_clamp_u32">; +defm DS_SUB_CLAMP_RTN_U32 : DS_1A1D_RET_mc<"ds_sub_clamp_rtn_u32", VGPR_32>; multiclass DSAtomicRetNoRetPatIntrinsic_mc { diff --git a/llvm/lib/Target/AMDGPU/FLATInstructions.td b/llvm/lib/Target/AMDGPU/FLATInstructions.td index 8a6016862426a..87bd682611521 100644 --- a/llvm/lib/Target/AMDGPU/FLATInstructions.td +++ b/llvm/lib/Target/AMDGPU/FLATInstructions.td @@ -541,8 +541,7 @@ multiclass FLAT_Atomic_Pseudo_NO_RTN< (outs), (ins VReg_64:$vaddr, data_op:$vdata, flat_offset:$offset, CPol_0:$cpol), " $vaddr, $vdata$offset$cpol">, - GlobalSaddrTable<0, opName>, - AtomicNoRet { + GlobalSaddrTable<0, opName> { let PseudoInstr = NAME; let FPAtomic = data_vt.isFP; let AddedComplexity = -1; // Prefer global atomics if available @@ -560,8 +559,7 @@ multiclass FLAT_Atomic_Pseudo_RTN< (outs getLdStRegisterOperand.ret:$vdst), (ins VReg_64:$vaddr, data_op:$vdata, flat_offset:$offset, CPol_GLC1:$cpol), " $vdst, $vaddr, $vdata$offset$cpol">, - GlobalSaddrTable<0, opName#"_rtn">, - AtomicNoRet { + GlobalSaddrTable<0, opName#"_rtn"> { let FPAtomic = data_vt.isFP; let AddedComplexity = -1; // Prefer global atomics if available } @@ -590,8 +588,7 @@ multiclass FLAT_Global_Atomic_Pseudo_NO_RTN< (outs), (ins VReg_64:$vaddr, data_op:$vdata, flat_offset:$offset, CPol_0:$cpol), " $vaddr, $vdata, off$offset$cpol">, - GlobalSaddrTable<0, opName>, - AtomicNoRet { + GlobalSaddrTable<0, opName> { let has_saddr = 1; let PseudoInstr = NAME; let FPAtomic = data_vt.isFP; @@ -601,8 +598,7 @@ multiclass FLAT_Global_Atomic_Pseudo_NO_RTN< (outs), (ins VGPR_32:$vaddr, data_op:$vdata, SReg_64:$saddr, flat_offset:$offset, CPol_0:$cpol), " $vaddr, $vdata, $saddr$offset$cpol">, - GlobalSaddrTable<1, opName>, - AtomicNoRet { + GlobalSaddrTable<1, opName> { let has_saddr = 1; let enabled_saddr = 1; let PseudoInstr = NAME#"_SADDR"; @@ -623,8 +619,7 @@ multiclass FLAT_Global_Atomic_Pseudo_RTN< (outs vdst_op:$vdst), (ins VReg_64:$vaddr, data_op:$vdata, flat_offset:$offset, CPol_GLC1:$cpol), " $vdst, $vaddr, $vdata, off$offset$cpol">, - GlobalSaddrTable<0, opName#"_rtn">, - AtomicNoRet { + GlobalSaddrTable<0, opName#"_rtn"> { let has_saddr = 1; let FPAtomic = data_vt.isFP; } @@ -633,8 +628,7 @@ multiclass FLAT_Global_Atomic_Pseudo_RTN< (outs vdst_op:$vdst), (ins VGPR_32:$vaddr, data_op:$vdata, SReg_64:$saddr, flat_offset:$offset, CPol_GLC1:$cpol), " $vdst, $vaddr, $vdata, $saddr$offset$cpol">, - GlobalSaddrTable<1, opName#"_rtn">, - AtomicNoRet { + GlobalSaddrTable<1, opName#"_rtn"> { let has_saddr = 1; let enabled_saddr = 1; let PseudoInstr = NAME#"_SADDR_RTN"; diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h index a8a33a5fecb41..82c6117292aee 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h @@ -1459,9 +1459,6 @@ namespace AMDGPU { LLVM_READONLY int getIfAddr64Inst(uint16_t Opcode); - LLVM_READONLY - int getAtomicNoRetOp(uint16_t Opcode); - LLVM_READONLY int getSOPKOp(uint16_t Opcode); diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td index 34cdb09b0e15d..835a5a2472315 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -2591,11 +2591,6 @@ class Commutable_REV { bit IsOrig = isOrig; } -class AtomicNoRet { - string NoRetOp = noRetOp; - bit IsRet = isRet; -} - //===----------------------------------------------------------------------===// // Interpolation opcodes //===----------------------------------------------------------------------===// @@ -2766,15 +2761,6 @@ def getIfAddr64Inst : InstrMapping { let ValueCols = [["1"]]; } -// Maps an atomic opcode to its returnless version. -def getAtomicNoRetOp : InstrMapping { - let FilterClass = "AtomicNoRet"; - let RowFields = ["NoRetOp"]; - let ColFields = ["IsRet"]; - let KeyCol = ["1"]; - let ValueCols = [["0"]]; -} - // Maps a GLOBAL to its SADDR form. def getGlobalSaddrOp : InstrMapping { let FilterClass = "GlobalSaddrTable"; diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td index 29651a8390399..a91fb87998fe5 100644 --- a/llvm/lib/Target/AMDGPU/SMInstructions.td +++ b/llvm/lib/Target/AMDGPU/SMInstructions.td @@ -277,8 +277,7 @@ class SM_Pseudo_Atomic, - AtomicNoRet { + isRet> { let has_offset = offsets.HasOffset; let has_soffset = offsets.HasSOffset; let PseudoInstr = opNameWithSuffix; @@ -662,8 +661,7 @@ defm S_ATC_PROBE_BUFFER : SM_Real_Probe_vi <0x27>; //===----------------------------------------------------------------------===// class SMEM_Atomic_Real_vi op, SM_Atomic_Pseudo ps> - : SMEM_Real_vi , - AtomicNoRet { + : SMEM_Real_vi { bits<7> sdata; @@ -1222,8 +1220,7 @@ defm S_ATC_PROBE : SM_Real_Probe_gfx10 <0x26>; defm S_ATC_PROBE_BUFFER : SM_Real_Probe_gfx10 <0x27>; class SMEM_Atomic_Real_gfx10 op, SM_Atomic_Pseudo ps> - : SMEM_Real_gfx10 , - AtomicNoRet { + : SMEM_Real_gfx10 { bits<7> sdata;