From 1d4994cc4d68cc7ee34ab5ca6f0c668a65f16e64 Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Thu, 25 Jan 2024 11:30:39 +0000 Subject: [PATCH 1/2] [AMDGPU] Do not bother adding reserved registers to liveins Tweak the implementation of llvm.amdgcn.wave.id to not add TTMP8 to the function liveins. --- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 4 +--- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 3 +-- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index e98ede88a7e2d..753c2f70f63fe 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -6890,11 +6890,9 @@ bool AMDGPULegalizerInfo::legalizeWaveID(MachineInstr &MI, return false; LLT S32 = LLT::scalar(32); Register DstReg = MI.getOperand(0).getReg(); - Register TTMP8 = - getFunctionLiveInPhysReg(B.getMF(), B.getTII(), AMDGPU::TTMP8, - AMDGPU::SReg_32RegClass, B.getDebugLoc(), S32); auto LSB = B.buildConstant(S32, 25); auto Width = B.buildConstant(S32, 5); + auto TTMP8 = B.buildCopy(S32, Register(AMDGPU::TTMP8)); B.buildUbfx(DstReg, TTMP8, LSB, Width); MI.eraseFromParent(); return true; diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 4cf9cafedf28f..ae0f0605a4a33 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -7927,8 +7927,7 @@ SDValue SITargetLowering::lowerWaveID(SelectionDAG &DAG, SDValue Op) const { return {}; SDLoc SL(Op); MVT VT = MVT::i32; - SDValue TTMP8 = CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass, - AMDGPU::TTMP8, VT, SL); + SDValue TTMP8 = DAG.getCopyFromReg(DAG.getEntryNode(), SL, AMDGPU::TTMP8, VT); return DAG.getNode(AMDGPUISD::BFE_U32, SL, VT, TTMP8, DAG.getConstant(25, SL, VT), DAG.getConstant(5, SL, VT)); } From bd5a4df2254d7932894ce1ea289bb959ad16eecd Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Thu, 25 Jan 2024 11:38:22 +0000 Subject: [PATCH 2/2] Tweak --- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index 753c2f70f63fe..17ffb7ec988f0 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -6890,9 +6890,9 @@ bool AMDGPULegalizerInfo::legalizeWaveID(MachineInstr &MI, return false; LLT S32 = LLT::scalar(32); Register DstReg = MI.getOperand(0).getReg(); + auto TTMP8 = B.buildCopy(S32, Register(AMDGPU::TTMP8)); auto LSB = B.buildConstant(S32, 25); auto Width = B.buildConstant(S32, 5); - auto TTMP8 = B.buildCopy(S32, Register(AMDGPU::TTMP8)); B.buildUbfx(DstReg, TTMP8, LSB, Width); MI.eraseFromParent(); return true;