From bdd6628bbacdd8d1070c459579a3c2608e1d8afd Mon Sep 17 00:00:00 2001 From: Mikhail Gudim Date: Wed, 2 Apr 2025 08:16:37 -0700 Subject: [PATCH 1/2] [RISCV] Add an option to enable CFIInstrInserter. --- llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 9 +++++++++ llvm/lib/Target/RISCV/RISCVFrameLowering.h | 3 +++ llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 10 +++++++++- 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp index b37b7405a660f..19524d016c06f 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -2507,3 +2507,12 @@ void RISCVFrameLowering::inlineStackProbe(MachineFunction &MF, } } } + +int RISCVFrameLowering::getInitialCFAOffset(const MachineFunction &MF) const { + return 0; +} + +Register +RISCVFrameLowering::getInitialCFARegister(const MachineFunction &MF) const { + return RISCV::X2; +} diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.h b/llvm/lib/Target/RISCV/RISCVFrameLowering.h index 6af63a4885f35..87980dfb09f96 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.h +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.h @@ -23,6 +23,9 @@ class RISCVFrameLowering : public TargetFrameLowering { public: explicit RISCVFrameLowering(const RISCVSubtarget &STI); + int getInitialCFAOffset(const MachineFunction &MF) const override; + Register getInitialCFARegister(const MachineFunction &MF) const override; + void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override; void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override; diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp index f81b1e1260ee3..077dbcc7d9003 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -103,6 +103,11 @@ static cl::opt cl::desc("Enable Machine Pipeliner for RISC-V"), cl::init(false), cl::Hidden); +static cl::opt EnableCFIInstrInserter( + "riscv-enable-cfi-instr-inserter", + cl::desc("Enable CFI Instruction Inserter for RISC-V"), cl::init(false), + cl::Hidden); + extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() { RegisterTargetMachine X(getTheRISCV32Target()); RegisterTargetMachine Y(getTheRISCV64Target()); @@ -169,7 +174,7 @@ RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT, if (TT.isOSFuchsia() && !TT.isArch64Bit()) report_fatal_error("Fuchsia is only supported for 64-bit"); - setCFIFixup(true); + setCFIFixup(!EnableCFIInstrInserter); } const RISCVSubtarget * @@ -576,6 +581,9 @@ void RISCVPassConfig::addPreEmitPass2() { addPass(createUnpackMachineBundles([&](const MachineFunction &MF) { return MF.getFunction().getParent()->getModuleFlag("kcfi"); })); + + if (EnableCFIInstrInserter) + addPass(createCFIInstrInserter()); } void RISCVPassConfig::addMachineSSAOptimization() { From edc42eb4135d3a30e9b7f00595bf7e5e66aab6ac Mon Sep 17 00:00:00 2001 From: Mikhail Gudim Date: Sat, 15 Nov 2025 01:30:16 -0800 Subject: [PATCH 2/2] added test --- llvm/test/CodeGen/RISCV/pipeline-options.ll | 35 +++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 llvm/test/CodeGen/RISCV/pipeline-options.ll diff --git a/llvm/test/CodeGen/RISCV/pipeline-options.ll b/llvm/test/CodeGen/RISCV/pipeline-options.ll new file mode 100644 index 0000000000000..26c9aaba09c94 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/pipeline-options.ll @@ -0,0 +1,35 @@ +; RUN: llc -mtriple=riscv64 -O3 \ +; RUN: -debug-pass=Structure < %s -o /dev/null 2>&1 | \ +; RUN: FileCheck %s --check-prefix=O3-WITHOUT-ENABLE-CFI-INSTR-INSERTER + +; RUN: llc -mtriple=riscv64 -O3 \ +; RUN: --riscv-enable-cfi-instr-inserter=true \ +; RUN: -debug-pass=Structure < %s -o /dev/null 2>&1 | \ +; RUN: FileCheck %s --check-prefix=O3-ENABLE-CFI-INSTR-INSERTER + +; RUN: llc -mtriple=riscv64 -O0 \ +; RUN: -debug-pass=Structure < %s -o /dev/null 2>&1 | \ +; RUN: FileCheck %s --check-prefix=O0-WITHOUT-ENABLE-CFI-INSTR-INSERTER + +; RUN: llc -mtriple=riscv64 -O0 \ +; RUN: --riscv-enable-cfi-instr-inserter=true \ +; RUN: -debug-pass=Structure < %s -o /dev/null 2>&1 | \ +; RUN: FileCheck %s --check-prefix=O0-ENABLE-CFI-INSTR-INSERTER + +; REQUIRES: asserts + +; O3-WITHOUT-ENABLE-CFI-INSTR-INSERTER-LABEL: Pass Arguments: +; NO-O3-WITHOUT-ENABLE-CFI-INSTR-INSERTER: Check CFA info and insert CFI instructions if needed +; O3-WITHOUT-ENABLE-CFI-INSTR-INSERTER: Insert CFI remember/restore state instructions + +; O3-ENABLE-CFI-INSTR-INSERTER-LABEL: Pass Arguments: +; O3-ENABLE-CFI-INSTR-INSERTER: Check CFA info and insert CFI instructions if needed +; NO-O3-ENABLE-CFI-INSTR-INSERTER: Insert CFI remember/restore state instructions + +; O0-WITHOUT-ENABLE-CFI-INSTR-INSERTER-LABEL: Pass Arguments: +; NO-O0-WITHOUT-ENABLE-CFI-INSTR-INSERTER: Check CFA info and insert CFI instructions if needed +; O0-WITHOUT-ENABLE-CFI-INSTR-INSERTER: Insert CFI remember/restore state instructions + +; O0-ENABLE-CFI-INSTR-INSERTER-LABEL: Pass Arguments: +; O0-ENABLE-CFI-INSTR-INSERTER: Check CFA info and insert CFI instructions if needed +; NO-O0-ENABLE-CFI-INSTR-INSERTER: Insert CFI remember/restore state instructions