From d509a24c20399336265cb8b2f9844accd361d0ba Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Wed, 15 Oct 2025 16:41:32 +0800 Subject: [PATCH] [X86][APX] Distinguish REX2 PUSH/POP from PPX --- .../llvm/Support/X86DisassemblerDecoderCommon.h | 1 + llvm/test/MC/Disassembler/X86/apx/pushp-popp.txt | 8 ++++++++ llvm/test/MC/X86/apx/pushp-popp-att.s | 8 +++++++- llvm/utils/TableGen/X86DisassemblerTables.cpp | 11 ++++++++--- llvm/utils/TableGen/X86RecognizableInstr.cpp | 2 ++ 5 files changed, 26 insertions(+), 4 deletions(-) diff --git a/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h b/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h index faaff4ad8ee02..4aa6c01d29cc2 100644 --- a/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h +++ b/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h @@ -121,6 +121,7 @@ enum attributeBits { "The Dynamic Duo! Prefer over all else because this changes " \ "most operands' meaning") \ ENUM_ENTRY(IC_64BIT_REX2, 2, "requires a REX2 prefix") \ + ENUM_ENTRY(IC_64BIT_REX2_REXW, 3, "requires a REX2 and the W prefix") \ ENUM_ENTRY(IC_VEX, 1, "requires a VEX prefix") \ ENUM_ENTRY(IC_VEX_XS, 2, "requires VEX and the XS prefix") \ ENUM_ENTRY(IC_VEX_XD, 2, "requires VEX and the XD prefix") \ diff --git a/llvm/test/MC/Disassembler/X86/apx/pushp-popp.txt b/llvm/test/MC/Disassembler/X86/apx/pushp-popp.txt index 4ec534fc9dcf6..fa40fe6581c38 100644 --- a/llvm/test/MC/Disassembler/X86/apx/pushp-popp.txt +++ b/llvm/test/MC/Disassembler/X86/apx/pushp-popp.txt @@ -17,6 +17,10 @@ # INTEL: pushp r16 0xd5,0x18,0x50 +# ATT: pushq %r16 +# INTEL: push r16 +0xd5,0x10,0x50 + # ATT: popp %rax # INTEL: popp rax 0xd5,0x08,0x58 @@ -32,3 +36,7 @@ # ATT: popp %r16 # INTEL: popp r16 0xd5,0x18,0x58 + +# ATT: popq %r16 +# INTEL: pop r16 +0xd5,0x10,0x58 diff --git a/llvm/test/MC/X86/apx/pushp-popp-att.s b/llvm/test/MC/X86/apx/pushp-popp-att.s index a8107448bb088..d638034f29f98 100644 --- a/llvm/test/MC/X86/apx/pushp-popp-att.s +++ b/llvm/test/MC/X86/apx/pushp-popp-att.s @@ -1,7 +1,7 @@ # RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s # RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR -# ERROR-COUNT-8: error: +# ERROR-COUNT-10: error: # ERROR-NOT: error: # CHECK: pushp %rax @@ -16,6 +16,9 @@ # CHECK: pushp %r16 # CHECK: encoding: [0xd5,0x18,0x50] pushp %r16 +# CHECK: pushq %r16 +# CHECK: encoding: [0xd5,0x10,0x50] + pushq %r16 # CHECK: popp %rax # CHECK: encoding: [0xd5,0x08,0x58] @@ -29,3 +32,6 @@ # CHECK: popp %r16 # CHECK: encoding: [0xd5,0x18,0x58] popp %r16 +# CHECK: popq %r16 +# CHECK: encoding: [0xd5,0x10,0x58] + popq %r16 diff --git a/llvm/utils/TableGen/X86DisassemblerTables.cpp b/llvm/utils/TableGen/X86DisassemblerTables.cpp index ed7a4fedbf730..3414190b9c9b4 100644 --- a/llvm/utils/TableGen/X86DisassemblerTables.cpp +++ b/llvm/utils/TableGen/X86DisassemblerTables.cpp @@ -99,6 +99,7 @@ static inline bool inheritsFrom(InstructionContext child, (noPrefix && inheritsFrom(child, IC_XS, noPrefix))); case IC_64BIT: return (inheritsFrom(child, IC_64BIT_REXW) || + inheritsFrom(child, IC_64BIT_REX2) || (noPrefix && inheritsFrom(child, IC_64BIT_OPSIZE, noPrefix)) || (!AdSize64 && inheritsFrom(child, IC_64BIT_ADSIZE)) || (noPrefix && inheritsFrom(child, IC_64BIT_XD, noPrefix)) || @@ -151,8 +152,10 @@ static inline bool inheritsFrom(InstructionContext child, case IC_64BIT_REXW_XS: case IC_64BIT_REXW_OPSIZE: case IC_64BIT_REXW_ADSIZE: - case IC_64BIT_REX2: + case IC_64BIT_REX2_REXW: return false; + case IC_64BIT_REX2: + return inheritsFrom(child, IC_64BIT_REX2_REXW); case IC_VEX: return (VEX_LIG && WIG && inheritsFrom(child, IC_VEX_L_W)) || (WIG && inheritsFrom(child, IC_VEX_W)) || @@ -980,9 +983,11 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const { if ((index & ATTR_EVEXB) && (index & ATTR_EVEXU)) o << "_U"; } - } else if ((index & ATTR_64BIT) && (index & ATTR_REX2)) + } else if ((index & ATTR_64BIT) && (index & ATTR_REX2)) { o << "IC_64BIT_REX2"; - else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS)) + if (index & ATTR_REXW) + o << "_REXW"; + } else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS)) o << "IC_64BIT_REXW_XS"; else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD)) o << "IC_64BIT_REXW_XD"; diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp index e87a1c9aa928e..a006888a2352c 100644 --- a/llvm/utils/TableGen/X86RecognizableInstr.cpp +++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp @@ -365,6 +365,8 @@ InstructionContext RecognizableInstr::insnContext() const { insnContext = IC_64BIT_XD; else if (OpPrefix == X86Local::XS) insnContext = IC_64BIT_XS; + else if (HasREX_W && ExplicitREX2Prefix) + insnContext = IC_64BIT_REX2_REXW; else if (ExplicitREX2Prefix) insnContext = IC_64BIT_REX2; else if (HasREX_W)