AMDGPU: Remove override of TargetInstrInfo::getRegClass

[arsenm]

This should not be overridable and the special case hacks
have been replaced with RegClassByHwMode

[arsenm]

• AMDGPU: Remove override of TargetInstrInfo::getRegClass #159886 👈 (View in Graphite)
• AMDGPU: Remove wrapper around TRI::getRegClass #159885
• AMDGPU: Start using RegClassByHwMode for wavesize operands  #159884
• AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints #158272 : 2 other dependent PRs (#158278 , #159880 )
• CodeGen: Add RegisterClass by HwMode #158269 : 4 other dependent PRs (#158271 , #158273 , #158274 and 1 other)
• main

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[llvmbot]

@llvm/pr-subscribers-llvm-globalisel

@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)

Changes

This should not be overridable and the special case hacks
have been replaced with RegClassByHwMode

---

Full diff: https://github.com/llvm/llvm-project/pull/159886.diff

2 Files Affected:

• (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (-13)
• (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.h (-4)

diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index a368a0de891ea..57698484d0bb7 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -5954,19 +5954,6 @@ SIInstrInfo::getWholeWaveFunctionSetup(MachineFunction &MF) const {
   llvm_unreachable("Couldn't find SI_SETUP_WHOLE_WAVE_FUNC instruction");
 }
 
-// FIXME: This should not be an overridable function. All subtarget dependent
-// operand modifications should go through isLookupRegClassByHwMode in the
-// generic handling.
-const TargetRegisterClass *
-SIInstrInfo::getRegClass(const MCInstrDesc &TID, unsigned OpNum,
-                         const TargetRegisterInfo *TRI) const {
-  if (OpNum >= TID.getNumOperands())
-    return nullptr;
-  const MCOperandInfo &OpInfo = TID.operands()[OpNum];
-  int16_t RegClass = getOpRegClassID(OpInfo);
-  return RegClass < 0 ? nullptr : RI.getRegClass(RegClass);
-}
-
 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
                                                       unsigned OpNo) const {
   const MCInstrDesc &Desc = get(MI.getOpcode());
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 48eb743c2e762..a9c1a8606ede1 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -1539,10 +1539,6 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
   /// Return true if this opcode should not be used by codegen.
   bool isAsmOnlyOpcode(int MCOp) const;
 
-  const TargetRegisterClass *
-  getRegClass(const MCInstrDesc &TID, unsigned OpNum,
-              const TargetRegisterInfo *TRI) const override;
-
   void fixImplicitOperands(MachineInstr &MI) const;
 
   MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,