From 9be8fd1a8079d25de86920764d913c59f490b77e Mon Sep 17 00:00:00 2001
From: Rajveer <rajveer.developer@icloud.com>
Date: Mon, 8 Sep 2025 15:43:24 +0530
Subject: [PATCH 1/2] [AArch64] Use unsigned variant of `<s|u>addv_64` SVE
 vector reduction intrinsic for 64 bit values

Resolves #157122

When lowering this intrinsic, we are querying the first result type (i.e `getValueType(0)`)
which may not always be true hence giving wrong the extended value type.
---
 .../Target/AArch64/AArch64ISelLowering.cpp    |  2 +-
 llvm/test/CodeGen/AArch64/sve-saddv_64.ll     | 23 +++++++++++++++++++
 2 files changed, 24 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/AArch64/sve-saddv_64.ll

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index aefbbe2534be2..24169f3f5a857 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -22396,7 +22396,7 @@ static SDValue performIntrinsicCombine(SDNode *N,
     return tryCombineCRC32(0xffff, N, DAG);
   case Intrinsic::aarch64_sve_saddv:
     // There is no i64 version of SADDV because the sign is irrelevant.
-    if (N->getOperand(2)->getValueType(0).getVectorElementType() == MVT::i64)
+    if (N->getOperand(2).getValueType().getVectorElementType() == MVT::i64)
       return combineSVEReductionInt(N, AArch64ISD::UADDV_PRED, DAG);
     else
       return combineSVEReductionInt(N, AArch64ISD::SADDV_PRED, DAG);
diff --git a/llvm/test/CodeGen/AArch64/sve-saddv_64.ll b/llvm/test/CodeGen/AArch64/sve-saddv_64.ll
new file mode 100644
index 0000000000000..900135c5121d7
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-saddv_64.ll
@@ -0,0 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+
+; Function Attrs: mustprogress nounwind ssp uwtable(sync) vscale_range(1,16)
+define noundef i64 @svaddv_SVBool_SVInt64_t(<vscale x 16 x i1> %a, <vscale x 2 x i64> %b) {
+; CHECK-LABEL: svaddv_SVBool_SVInt64_t:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    //APP
+; CHECK-NEXT:    //NO_APP
+; CHECK-NEXT:    uaddv d0, p0, z0.d
+; CHECK-NEXT:    fmov x0, d0
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call { <vscale x 16 x i1>, <vscale x 2 x i64> } asm sideeffect "", "=@3Upa,=w,0,1"(<vscale x 16 x i1> %a, <vscale x 2 x i64> %b)
+  %asmresult = extractvalue { <vscale x 16 x i1>, <vscale x 2 x i64> } %0, 0
+  %asmresult1 = extractvalue { <vscale x 16 x i1>, <vscale x 2 x i64> } %0, 1
+  %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %asmresult)
+  %2 = tail call i64 @llvm.aarch64.sve.saddv.nxv2i64(<vscale x 2 x i1> %1, <vscale x 2 x i64> %asmresult1)
+  ret i64 %2
+}
+
+declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>)
+declare i64 @llvm.aarch64.sve.saddv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>)

From 51029790a52d1f543a8c8061b71b023e664e7e7a Mon Sep 17 00:00:00 2001
From: Rajveer Singh Bharadwaj <rajveer.developer@icloud.com>
Date: Tue, 9 Sep 2025 11:16:31 +0530
Subject: [PATCH 2/2] Address minor comments

---
 llvm/test/CodeGen/AArch64/sve-saddv_64.ll | 1 -
 1 file changed, 1 deletion(-)

diff --git a/llvm/test/CodeGen/AArch64/sve-saddv_64.ll b/llvm/test/CodeGen/AArch64/sve-saddv_64.ll
index 900135c5121d7..f30477805262b 100644
--- a/llvm/test/CodeGen/AArch64/sve-saddv_64.ll
+++ b/llvm/test/CodeGen/AArch64/sve-saddv_64.ll
@@ -1,7 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
 
-; Function Attrs: mustprogress nounwind ssp uwtable(sync) vscale_range(1,16)
 define noundef i64 @svaddv_SVBool_SVInt64_t(<vscale x 16 x i1> %a, <vscale x 2 x i64> %b) {
 ; CHECK-LABEL: svaddv_SVBool_SVInt64_t:
 ; CHECK:       // %bb.0: // %entry