From 7c8e165ca068cb9508928ed76611cc0582c0ef70 Mon Sep 17 00:00:00 2001 From: Shreeyash Pandey Date: Mon, 25 Aug 2025 16:59:13 +0530 Subject: [PATCH 1/6] [RISCV] add computeKnownBitsForTargetNode for RISCVISD::SRLW Signed-off-by: Shreeyash Pandey --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 9 ++ llvm/unittests/Target/RISCV/CMakeLists.txt | 1 + .../Target/RISCV/RISCVSelectionDAGTest.cpp | 109 ++++++++++++++++++ 3 files changed, 119 insertions(+) create mode 100644 llvm/unittests/Target/RISCV/RISCVSelectionDAGTest.cpp diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 4a1db80076530..6dacd83bfe550 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -21340,6 +21340,15 @@ void RISCVTargetLowering::computeKnownBitsForTargetNode(const SDValue Op, Known = Known.sext(BitWidth); break; } + case RISCVISD::SRLW: { + KnownBits Known2; + Known = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1); + Known2 = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1); + Known = KnownBits::lshr(Known.trunc(32), Known2.trunc(5).zext(32)); + // Restore the original width by sign extending. + Known = Known.sext(BitWidth); + break; + } case RISCVISD::CTZW: { KnownBits Known2 = DAG.computeKnownBits(Op.getOperand(0), Depth + 1); unsigned PossibleTZ = Known2.trunc(32).countMaxTrailingZeros(); diff --git a/llvm/unittests/Target/RISCV/CMakeLists.txt b/llvm/unittests/Target/RISCV/CMakeLists.txt index 8da8c3896faf1..701bbee55da71 100644 --- a/llvm/unittests/Target/RISCV/CMakeLists.txt +++ b/llvm/unittests/Target/RISCV/CMakeLists.txt @@ -19,4 +19,5 @@ set(LLVM_LINK_COMPONENTS add_llvm_target_unittest(RISCVTests MCInstrAnalysisTest.cpp RISCVInstrInfoTest.cpp + RISCVSelectionDAGTest.cpp ) diff --git a/llvm/unittests/Target/RISCV/RISCVSelectionDAGTest.cpp b/llvm/unittests/Target/RISCV/RISCVSelectionDAGTest.cpp new file mode 100644 index 0000000000000..a13f88484c00c --- /dev/null +++ b/llvm/unittests/Target/RISCV/RISCVSelectionDAGTest.cpp @@ -0,0 +1,109 @@ +//===----------------------------------------------------------------------===// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "RISCVISelLowering.h" +#include "llvm/Analysis/OptimizationRemarkEmitter.h" +#include "llvm/AsmParser/Parser.h" +#include "llvm/CodeGen/MachineModuleInfo.h" +#include "llvm/CodeGen/SelectionDAG.h" +#include "llvm/CodeGen/TargetLowering.h" +#include "llvm/IR/MDBuilder.h" +#include "llvm/IR/Module.h" +#include "llvm/MC/TargetRegistry.h" +#include "llvm/Support/KnownBits.h" +#include "llvm/Support/SourceMgr.h" +#include "llvm/Support/TargetSelect.h" +#include "llvm/Support/raw_ostream.h" +#include "llvm/Target/TargetMachine.h" +#include "gtest/gtest.h" + +namespace llvm { + +class RISCVSelectionDAGTest : public testing::Test { + +protected: + static void SetUpTestCase() { + LLVMInitializeRISCVTargetInfo(); + LLVMInitializeRISCVTarget(); + LLVMInitializeRISCVTargetMC(); + } + + void SetUp() override { + StringRef Assembly = "define void @f() { ret void }"; + + Triple TargetTriple("riscv64", "unknown", "linux"); + + std::string Error; + const Target *T = TargetRegistry::lookupTarget("", TargetTriple, Error); + + TargetOptions Options; + TM = std::unique_ptr(T->createTargetMachine( + TargetTriple, "generic", "", Options, std::nullopt, std::nullopt, + CodeGenOptLevel::Default)); + + SMDiagnostic SMError; + M = parseAssemblyString(Assembly, SMError, Context); + if (!M) + report_fatal_error(SMError.getMessage()); + M->setDataLayout(TM->createDataLayout()); + + F = M->getFunction("f"); + if (!F) + report_fatal_error("Function 'f' not found"); + + MachineModuleInfo MMI(TM.get()); + + MF = std::make_unique(*F, *TM, *TM->getSubtargetImpl(*F), + MMI.getContext(), /*FunctionNum*/ 0); + + DAG = std::make_unique(*TM, CodeGenOptLevel::None); + if (!DAG) + report_fatal_error("SelectionDAG allocation failed"); + + OptimizationRemarkEmitter ORE(F); + DAG->init(*MF, ORE, /*LibInfo*/ nullptr, /*AA*/ nullptr, + /*AC*/ nullptr, /*MDT*/ nullptr, /*MSDT*/ nullptr, MMI, nullptr); + } + + LLVMContext Context; + std::unique_ptr TM; + std::unique_ptr M; + Function *F = nullptr; + std::unique_ptr MF; + std::unique_ptr DAG; +}; + +/// SRLW: Logical Shift Right +TEST_F(RISCVSelectionDAGTest, computeKnownBits_SRLW) { + // Following DAG is created from this IR snippet: + // + // define i64 @f(i32 %x, i32 %y) { + // %a = and i32 %x, 2147483647 ; zeros the MSB for %x + // %b = lshr i32 %a, %y + // %c = zext i32 %b to i64 ; makes the most significant 32 bits 0 + // ret i64 %c + // } + SDLoc Loc; + auto IntVT = EVT::getIntegerVT(Context, 32); + auto Int64VT = EVT::getIntegerVT(Context, 64); + auto Px = DAG->getRegister(0, IntVT); + auto Py = DAG->getConstant(2147483647, Loc, IntVT); + auto N1 = DAG->getNode(ISD::AND, Loc, IntVT, Px, Py); + auto Qx = DAG->getRegister(0, IntVT); + auto N2 = DAG->getNode(ISD::SRL, Loc, IntVT, N1, Qx); + auto N3 = DAG->getNode(ISD::ZERO_EXTEND, Loc, Int64VT, N2); + // N1 = 0??????????????????????????????? + // N2 = 0??????????????????????????????? + // N3 = 000000000000000000000000000000000??????????????????????????????? + // After zero extend, we expect 33 most significant zeros to be known: + // 32 from sign extension and 1 from AND operation + KnownBits Known = DAG->computeKnownBits(N3); + EXPECT_EQ(Known.Zero, APInt(64, -2147483648)); + EXPECT_EQ(Known.One, APInt(64, 0)); +} + +} // end namespace llvm From d713682b7a6a5fcc81428ae2fcc958d14f83e770 Mon Sep 17 00:00:00 2001 From: Shreeyash Pandey Date: Sat, 30 Aug 2025 17:36:17 +0530 Subject: [PATCH 2/6] [RISCV] use RISCVISD::SRLW instead of the generic ISD:SRL Signed-off-by: Shreeyash Pandey --- llvm/unittests/Target/RISCV/RISCVSelectionDAGTest.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/llvm/unittests/Target/RISCV/RISCVSelectionDAGTest.cpp b/llvm/unittests/Target/RISCV/RISCVSelectionDAGTest.cpp index a13f88484c00c..c6779e6f7b86a 100644 --- a/llvm/unittests/Target/RISCV/RISCVSelectionDAGTest.cpp +++ b/llvm/unittests/Target/RISCV/RISCVSelectionDAGTest.cpp @@ -6,6 +6,7 @@ //===----------------------------------------------------------------------===// #include "RISCVISelLowering.h" +#include "RISCVSelectionDAGInfo.h" #include "llvm/Analysis/OptimizationRemarkEmitter.h" #include "llvm/AsmParser/Parser.h" #include "llvm/CodeGen/MachineModuleInfo.h" @@ -94,7 +95,7 @@ TEST_F(RISCVSelectionDAGTest, computeKnownBits_SRLW) { auto Py = DAG->getConstant(2147483647, Loc, IntVT); auto N1 = DAG->getNode(ISD::AND, Loc, IntVT, Px, Py); auto Qx = DAG->getRegister(0, IntVT); - auto N2 = DAG->getNode(ISD::SRL, Loc, IntVT, N1, Qx); + auto N2 = DAG->getNode(RISCVISD::SRLW, Loc, IntVT, N1, Qx); auto N3 = DAG->getNode(ISD::ZERO_EXTEND, Loc, Int64VT, N2); // N1 = 0??????????????????????????????? // N2 = 0??????????????????????????????? From f3833cd75cc20f231c4f6dd2f32790eaad8922b1 Mon Sep 17 00:00:00 2001 From: Shreeyash Pandey Date: Sat, 30 Aug 2025 22:49:49 +0530 Subject: [PATCH 3/6] [RISCV] make SRLW io types be 64 bits Signed-off-by: Shreeyash Pandey --- llvm/unittests/Target/RISCV/RISCVSelectionDAGTest.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/unittests/Target/RISCV/RISCVSelectionDAGTest.cpp b/llvm/unittests/Target/RISCV/RISCVSelectionDAGTest.cpp index c6779e6f7b86a..55fe665dcbadd 100644 --- a/llvm/unittests/Target/RISCV/RISCVSelectionDAGTest.cpp +++ b/llvm/unittests/Target/RISCV/RISCVSelectionDAGTest.cpp @@ -94,8 +94,8 @@ TEST_F(RISCVSelectionDAGTest, computeKnownBits_SRLW) { auto Px = DAG->getRegister(0, IntVT); auto Py = DAG->getConstant(2147483647, Loc, IntVT); auto N1 = DAG->getNode(ISD::AND, Loc, IntVT, Px, Py); - auto Qx = DAG->getRegister(0, IntVT); - auto N2 = DAG->getNode(RISCVISD::SRLW, Loc, IntVT, N1, Qx); + auto Qx = DAG->getRegister(0, Int64VT); + auto N2 = DAG->getNode(RISCVISD::SRLW, Loc, Int64VT, N1, Qx); auto N3 = DAG->getNode(ISD::ZERO_EXTEND, Loc, Int64VT, N2); // N1 = 0??????????????????????????????? // N2 = 0??????????????????????????????? From 04eb8c3626eb85041949a084b51549fcf865ec79 Mon Sep 17 00:00:00 2001 From: Shreeyash Pandey Date: Sun, 31 Aug 2025 16:42:54 +0530 Subject: [PATCH 4/6] [RISCV] re-write DAG generation based on actual DAG output Signed-off-by: Shreeyash Pandey --- .../Target/RISCV/RISCVSelectionDAGTest.cpp | 58 +++++++++++++------ 1 file changed, 41 insertions(+), 17 deletions(-) diff --git a/llvm/unittests/Target/RISCV/RISCVSelectionDAGTest.cpp b/llvm/unittests/Target/RISCV/RISCVSelectionDAGTest.cpp index 55fe665dcbadd..f9e3416076b49 100644 --- a/llvm/unittests/Target/RISCV/RISCVSelectionDAGTest.cpp +++ b/llvm/unittests/Target/RISCV/RISCVSelectionDAGTest.cpp @@ -80,28 +80,52 @@ class RISCVSelectionDAGTest : public testing::Test { /// SRLW: Logical Shift Right TEST_F(RISCVSelectionDAGTest, computeKnownBits_SRLW) { - // Following DAG is created from this IR snippet: + // Given the following IR snippet: + // define i64 @f(i32 %x, i32 %y) { + // %a = and i32 %x, 2147483647 ; zeros the MSB for %x + // %b = lshr i32 %a, %y + // %c = zext i32 %b to i64 ; makes the most significant 32 bits 0 + // ret i64 %c + // } + // The Optimized SelectionDAG as show by llc -mtriple="riscv64" -debug-only=isel-dump + // is: + // t0: ch,glue = EntryToken + // t2: i64,ch = CopyFromReg t0, Register:i64 %0 + // t18: i64 = and t2, Constant:i64<2147483647> + // t4: i64,ch = CopyFromReg t0, Register:i64 %1 + // t20: i64 = RISCVISD::SRLW t18, t4 + // t22: i64 = and t20, Constant:i64<4294967295> + // t13: ch,glue = CopyToReg t0, Register:i64 $x10, t22 + // t14: ch = RISCVISD::RET_GLUE t13, Register:i64 $x10, t13:1 // - // define i64 @f(i32 %x, i32 %y) { - // %a = and i32 %x, 2147483647 ; zeros the MSB for %x - // %b = lshr i32 %a, %y - // %c = zext i32 %b to i64 ; makes the most significant 32 bits 0 - // ret i64 %c - // } + // The DAG created below is derived from this SDLoc Loc; - auto IntVT = EVT::getIntegerVT(Context, 32); auto Int64VT = EVT::getIntegerVT(Context, 64); - auto Px = DAG->getRegister(0, IntVT); - auto Py = DAG->getConstant(2147483647, Loc, IntVT); - auto N1 = DAG->getNode(ISD::AND, Loc, IntVT, Px, Py); + auto Px = DAG->getRegister(0, Int64VT); + auto Py = DAG->getConstant(2147483647, Loc, Int64VT); + auto N1 = DAG->getNode(ISD::AND, Loc, Int64VT, Px, Py); auto Qx = DAG->getRegister(0, Int64VT); auto N2 = DAG->getNode(RISCVISD::SRLW, Loc, Int64VT, N1, Qx); - auto N3 = DAG->getNode(ISD::ZERO_EXTEND, Loc, Int64VT, N2); - // N1 = 0??????????????????????????????? - // N2 = 0??????????????????????????????? - // N3 = 000000000000000000000000000000000??????????????????????????????? - // After zero extend, we expect 33 most significant zeros to be known: - // 32 from sign extension and 1 from AND operation + auto Py2 = DAG->getConstant(4294967295, Loc, Int64VT); + auto N3 = DAG->getNode(ISD::AND, Loc, Int64VT, N2, Py2); + // N1 = Px & 0x7FFFFFFF + // The first AND ensures that the input to the shift has bit 31 cleared. + // This means bits [63:31] of N1 are known to be zero. + // + // N2 = SRLW N1, Qx + // SRLW performs a 32-bit logical right shift and then sign-extends the + // 32-bit result to 64 bits. Because we know N1's bit 31 is 0, the + // 32-bit result of the shift will also have its sign bit (bit 31) as 0. + // Therefore, the sign-extension is guaranteed to be a zero-extension. + // + // N3 = N2 & 0xFFFFFFFF + // This second AND is part of the canonical pattern to clear the upper + // 32 bits, explicitly performing the zero-extension. From a KnownBits + // perspective, it's redundant, as N2's upper bits are already known zero. + // + // As a result, for N3, we know the upper 32 bits are zero (from the effective + // zero-extension) and we also know bit 31 is zero (from the initial AND). + // This gives us 33 known most-significant zero bits. KnownBits Known = DAG->computeKnownBits(N3); EXPECT_EQ(Known.Zero, APInt(64, -2147483648)); EXPECT_EQ(Known.One, APInt(64, 0)); From 69d9c85f542a067252bf91fd8361e3bba797f3ab Mon Sep 17 00:00:00 2001 From: Shreeyash Pandey Date: Mon, 1 Sep 2025 15:44:03 +0530 Subject: [PATCH 5/6] [RISCV] fix formatting for RISCVSelectionDAGTest.cpp Signed-off-by: Shreeyash Pandey --- llvm/unittests/Target/RISCV/RISCVSelectionDAGTest.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/unittests/Target/RISCV/RISCVSelectionDAGTest.cpp b/llvm/unittests/Target/RISCV/RISCVSelectionDAGTest.cpp index f9e3416076b49..f6b8ca7256554 100644 --- a/llvm/unittests/Target/RISCV/RISCVSelectionDAGTest.cpp +++ b/llvm/unittests/Target/RISCV/RISCVSelectionDAGTest.cpp @@ -87,8 +87,8 @@ TEST_F(RISCVSelectionDAGTest, computeKnownBits_SRLW) { // %c = zext i32 %b to i64 ; makes the most significant 32 bits 0 // ret i64 %c // } - // The Optimized SelectionDAG as show by llc -mtriple="riscv64" -debug-only=isel-dump - // is: + // The Optimized SelectionDAG as show by llc -mtriple="riscv64" + // -debug-only=isel-dump is: // t0: ch,glue = EntryToken // t2: i64,ch = CopyFromReg t0, Register:i64 %0 // t18: i64 = and t2, Constant:i64<2147483647> From 14cc218fd603581ce997bbc9f61c4e10a25741d9 Mon Sep 17 00:00:00 2001 From: Shreeyash Pandey Date: Wed, 3 Sep 2025 17:33:26 +0530 Subject: [PATCH 6/6] [RISCV] add a missing brace in RISCVISelLowering.cpp Signed-off-by: Shreeyash Pandey --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 7fc26c6999b9e..b5e493691f6a4 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -21387,6 +21387,7 @@ void RISCVTargetLowering::computeKnownBitsForTargetNode(const SDValue Op, // Restore the original width by sign extending. Known = Known.sext(BitWidth); break; + } case RISCVISD::SRAW: { KnownBits Known2; Known = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);