Skip to content

[test] Add missing tests for Arm frexpf128 and Mips ldexpf128 #148793

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Jul 15, 2025
Merged

[test] Add missing tests for Arm frexpf128 and Mips ldexpf128 #148793

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
53 changes: 53 additions & 0 deletions llvm/test/CodeGen/ARM/llvm.frexp.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -544,6 +544,59 @@ define <2 x i32> @test_frexp_v2f64_v2i32_only_use_exp(<2 x double> %a) {
ret <2 x i32> %result.1
}

define { fp128, i32 } @test_frexp_f128_i32(fp128 %a) nounwind {
; CHECK-LABEL: test_frexp_f128_i32:
; CHECK: @ %bb.0:
; CHECK-NEXT: push {r4, lr}
; CHECK-NEXT: sub sp, #8
; CHECK-NEXT: mov r12, r3
; CHECK-NEXT: ldr r3, [sp, #16]
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: add r0, sp, #4
; CHECK-NEXT: str r0, [sp]
; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: mov r1, r2
; CHECK-NEXT: mov r2, r12
; CHECK-NEXT: bl frexpl
; CHECK-NEXT: ldr.w r12, [sp, #4]
; CHECK-NEXT: stm.w r4, {r0, r1, r2, r3, r12}
; CHECK-NEXT: add sp, #8
; CHECK-NEXT: pop {r4, pc}
%result = call { fp128, i32 } @llvm.frexp.f128.i32(fp128 %a)
ret { fp128, i32 } %result
}

define fp128 @test_frexp_f128_i32_only_use_fract(fp128 %a) nounwind {
; CHECK-LABEL: test_frexp_f128_i32_only_use_fract:
; CHECK: @ %bb.0:
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: sub sp, #8
; CHECK-NEXT: add.w r12, sp, #4
; CHECK-NEXT: str.w r12, [sp]
; CHECK-NEXT: bl frexpl
; CHECK-NEXT: add sp, #8
; CHECK-NEXT: pop {r7, pc}
%result = call { fp128, i32 } @llvm.frexp.f128.i32(fp128 %a)
%result.0 = extractvalue { fp128, i32 } %result, 0
ret fp128 %result.0
}

define i32 @test_frexp_f128_i32_only_use_exp(fp128 %a) nounwind {
; CHECK-LABEL: test_frexp_f128_i32_only_use_exp:
; CHECK: @ %bb.0:
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: sub sp, #8
; CHECK-NEXT: add.w r12, sp, #4
; CHECK-NEXT: str.w r12, [sp]
; CHECK-NEXT: bl frexpl
; CHECK-NEXT: ldr r0, [sp, #4]
; CHECK-NEXT: add sp, #8
; CHECK-NEXT: pop {r7, pc}
%result = call { fp128, i32 } @llvm.frexp.f128.i32(fp128 %a)
%result.0 = extractvalue { fp128, i32 } %result, 1
ret i32 %result.0
}

declare { float, i32 } @llvm.frexp.f32.i32(float) #0
declare { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float>) #0
declare { <4 x float>, <4 x i32> } @llvm.frexp.v4f32.v4i32(<4 x float>) #0
Expand Down
15 changes: 15 additions & 0 deletions llvm/test/CodeGen/Mips/ldexp.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -125,6 +125,21 @@ define half @ldexp_f16(half %arg0, i32 %arg1) nounwind {
ret half %ldexp
}

define fp128 @ldexp_f128(fp128 %arg0, i32 %arg1) nounwind {
; SOFT-LABEL: ldexp_f128:
; SOFT: # %bb.0:
; SOFT-NEXT: addiu $sp, $sp, -32
; SOFT-NEXT: sw $ra, 28($sp) # 4-byte Folded Spill
; SOFT-NEXT: lw $1, 48($sp)
; SOFT-NEXT: jal ldexpl
; SOFT-NEXT: sw $1, 16($sp)
; SOFT-NEXT: lw $ra, 28($sp) # 4-byte Folded Reload
; SOFT-NEXT: jr $ra
; SOFT-NEXT: addiu $sp, $sp, 32
%ldexp = call fp128 @llvm.ldexp.f128.i32(fp128 %arg0, i32 %arg1)
ret fp128 %ldexp
}

declare double @llvm.ldexp.f64.i32(double, i32) #0
declare float @llvm.ldexp.f32.i32(float, i32) #0
declare <2 x float> @llvm.ldexp.v2f32.v2i32(<2 x float>, <2 x i32>) #0
Expand Down
Loading