[RISCV] Guard the alternative static chain register use on ILP32E/LP64E #142715
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
|
@llvm/pr-subscribers-backend-risc-v Author: Jesse Huang (jaidTw) ChangesFull diff: https://github.com/llvm/llvm-project/pull/142715.diff 1 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVCallingConv.cpp b/llvm/lib/Target/RISCV/RISCVCallingConv.cpp
index e0d1fb2facc87..3b609adcf8c09 100644
--- a/llvm/lib/Target/RISCV/RISCVCallingConv.cpp
+++ b/llvm/lib/Target/RISCV/RISCVCallingConv.cpp
@@ -338,6 +338,10 @@ bool llvm::CC_RISCV(unsigned ValNo, MVT ValVT, MVT LocVT,
bool HasCFBranch =
Subtarget.hasStdExtZicfilp() &&
MF.getFunction().getParent()->getModuleFlag("cf-protection-branch");
+ if (HasCFBranch && (Subtarget.isRV32() && Subtarget.hasStdExtE()))
+ reportFatalUsageError(
+ "Alternative static chain register is not supported on RV32E");
+
// Normal: t2, Branch control flow protection: t3
const auto StaticChainReg = HasCFBranch ? RISCV::X28 : RISCV::X7;
|
topperc
reviewed
Jun 4, 2025
kito-cheng
reviewed
Jun 4, 2025
Co-authored-by: Kito Cheng <[email protected]>
|
✅ With the latest revision this PR passed the C/C++ code formatter. |
jaidTw
changed the title
|
ping |
|
Can we have a test for this? You use the |
lenary
reviewed
Jun 10, 2025
Co-authored-by: Sam Elliott <[email protected]>
lenary
approved these changes
Jun 11, 2025
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/157/builds/30527 Here is the relevant piece of the build log for the reference |
tomtor
pushed a commit
to tomtor/llvm-project
that referenced
this pull request
Jun 14, 2025
…4E (llvm#142715) Asserts the use of t3(x28) as the static chain register when branch control flow protection is enabled with ILP32E/LP64E, because such register is not present within the ABI.
akuhlens
pushed a commit
to akuhlens/llvm-project
that referenced
this pull request
Jun 24, 2025
…4E (llvm#142715) Asserts the use of t3(x28) as the static chain register when branch control flow protection is enabled with ILP32E/LP64E, because such register is not present within the ABI.
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
No description provided.