diff --git a/llvm/lib/Target/PowerPC/PPCInstrP10.td b/llvm/lib/Target/PowerPC/PPCInstrP10.td index d295f35fb1dd0..39165f9122ea1 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrP10.td +++ b/llvm/lib/Target/PowerPC/PPCInstrP10.td @@ -2159,8 +2159,138 @@ let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX] in { (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; } -class XXEvalPattern imm> : - Pat<(v4i32 pattern), (XXEVAL $vA, $vB, $vC, imm)> {} + // ============================================================================= + // XXEVAL Instruction Pattern Definitions + // ============================================================================= + // + // XXEVAL instruction performs 256 different logical operations on three vector + // operands using an 8-bit immediate value to select the operation. + // Format: xxeval XT, XA, XB, XC, IMM + // For example: + // Equivalent function A?xor(B,C):and(B,C) is performed if the IMM value is 22. + // + // REGISTER CLASS CONSTRAINTS: + // - XXEVAL natively supports: VSRC register class [v4i32, v4f32, v2f64, v2i64] + // - Other vector types [v16i8, v8i16] require COPY_TO_REGCLASS to/from VRRC + // + // PATTERN STRATEGY: + // - XXEvalPattern: Class that automatically handles VSRC/VRRC conversion. + // ============================================================================= + + // Auto-detect if type needs VRRC register class conversion +class IsVRRCType { + bit Res = !or(!eq(Vt, v8i16), !eq(Vt, v16i8)); +} + // Defines a helper class that automatically handles both VSRC and VRRC types +class XXEvalPattern Imm> { + dag Instr = !if(IsVRRCType.Res, + // VRRC path: wrap with COPY_TO_REGCLASS + (COPY_TO_REGCLASS + (XXEVAL (COPY_TO_REGCLASS Vt:$vA, VSRC), + (COPY_TO_REGCLASS Vt:$vB, VSRC), + (COPY_TO_REGCLASS Vt:$vC, VSRC), Imm), VRRC), + // VSRC path: direct XXEVAL + (XXEVAL $vA, $vB, $vC, Imm)); +} + + // ============================================================================= + // Helper Classes abstract the complexity of handling both XXEVAL-native types + // (v4i32, v2i64) and non-native types (v8i16, v16i8) that require bitcasting. + // + // BITCASTING STRATEGY: + // - For v4i32: Use operation directly (no bitcast needed) + // - For other types: Bit operations happens in v4i32 and requires bitcasting. + // bitcast → v4i32 → operation → bitcast back to original type + // ============================================================================= + + // ============================================================================= + // Generates bitcast-aware unary NOT operations for any vector type. + // Handles the type conversion complexity transparently. + // + // USAGE: Not.B generates vnot for $vB operand of type v8i16 + // Not.C generates vnot for $vC operand of type v8i16 +class Not { + // NOT operation on $vB operand, with type-appropriate bitcasting + dag B = !if(!eq(Vt, v4i32), + (vnot Vt:$vB), // Direct: v4i32 native + (Vt (bitconvert (vnot (v4i32 (bitconvert Vt:$vB)))))); // Bitcast: other types + + // NOT operation on $vC operand, with type-appropriate bitcasting + dag C = !if(!eq(Vt, v4i32), + (vnot Vt:$vC), // Direct: v4i32 native + (Vt (bitconvert (vnot (v4i32 (bitconvert Vt:$vC)))))); // Bitcast: other types +} + + // ============================================================================= + // Generates bitcast-aware binary operations (and, or, xor) for any vector type. + // Supports optional logical inversion of the result (for NOR, EQV operations). + // + // PARAMETERS: + // Vt: Vector type (v4i32, v8i16, v16i8, v2i64) + // Op: Binary operation (and, or, xor) + // Negate: 0=direct operation, 1=NOT(operation) for NOR/EQV patterns + // + // USAGE: XXEvalBinOp.BC // XOR of two v8i16 operands + // XXEvalBinOp.BC // NOR of two v8i16 operands (or + not) +class XXEvalBinOp { + dag BC = !if(!eq(Negate, 0), + // Direct binary operation (and, or, xor) + !if(!eq(Vt, v4i32), + (Op Vt:$vB, Vt:$vC), // Direct: v4i32 native + (Vt (bitconvert (Op (v4i32 (bitconvert Vt:$vB)), // Bitcast: other types + (v4i32 (bitconvert Vt:$vC)))))), + // Inverted binary operation (nor, eqv) + !if(!eq(Vt, v4i32), + (vnot (Op Vt:$vB, Vt:$vC)), // Direct: v4i32 native + (Vt (bitconvert (vnot (Op (v4i32 (bitconvert Vt:$vB)), // Bitcast: other types + (v4i32 (bitconvert Vt:$vC)))))))); +} + // ============================================================================= + // Pattern class for common binary bit operations +class And : XXEvalBinOp; +class Or : XXEvalBinOp; +class Xor : XXEvalBinOp; +class Nor : XXEvalBinOp; // not(or) +class Eqv : XXEvalBinOp; // not(xor) + + // ============================================================================= + // XXEVAL Ternary Pattern Multiclasses + // ============================================================================= + // + // These multiclasses generate patterns for XXEVAL instructions that implement + // complex ternary equivalent operations of the form: vselect(A, f(B,C), g(B,C)) + // + // The specific immediate values correspond to PowerPC XXEVAL instruction + // encodings for various ternary equivalent operations. + // ============================================================================= + + // Generates XXEVAL patterns for bot VSRC and VRRC types using XXEvalPattern class + // Implements: vselect(A, , and(B,C)) + // include and(B,C), xor(B,C), nor(B,C), eqv(B,C), not(C), not(B) + // + // SUPPORTED TYPES: v4i32, v2i64, v16i8, v8i16 + // IMMEDIATE ENCODING determines the ternary equivalent operation of xxeval instruction. +multiclass XXEvalXAnd { + /// vselect(A, xor(B,C), and(B,C)) : xxeval Imm Value is 22 + def : Pat<(Vt (vselect Vt:$vA, Xor.BC, And.BC)), + XXEvalPattern.Instr>; + + // vselect(A, nor(B,C), and(B,C)) : xxeval Imm Value is 24 + def : Pat<(Vt (vselect Vt:$vA, Nor.BC, And.BC)), + XXEvalPattern.Instr>; + + // vselect(A, eqv(B,C), and(B,C)) : xxeval Imm Value is 25 + def : Pat<(Vt (vselect Vt:$vA, Eqv.BC, And.BC)), + XXEvalPattern.Instr>; + + // vselect(A, not(C), and(B,C)) : xxeval Imm Value is 26 + def : Pat<(Vt (vselect Vt:$vA, Not.C, And.BC)), + XXEvalPattern.Instr>; + + // vselect(A, not(B), and(B,C)) : xxeval Imm Value is 28 + def : Pat<(Vt (vselect Vt:$vA, Not.B, And.BC)), + XXEvalPattern.Instr>; +} let Predicates = [PrefixInstrs, HasP10Vector] in { let AddedComplexity = 400 in { @@ -2192,83 +2322,88 @@ let Predicates = [PrefixInstrs, HasP10Vector] in { // Anonymous patterns for XXEVAL // AND // and(A, B, C) - def : XXEvalPattern<(and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 1>; - // and(A, xor(B, C)) - def : XXEvalPattern<(and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 6>; - // and(A, or(B, C)) - def : XXEvalPattern<(and v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 7>; - // and(A, nor(B, C)) - def : XXEvalPattern<(and v4i32:$vA, (vnot (or v4i32:$vB, v4i32:$vC))), 8>; - // and(A, eqv(B, C)) - def : XXEvalPattern<(and v4i32:$vA, (vnot (xor v4i32:$vB, v4i32:$vC))), 9>; - // and(A, nand(B, C)) - def : XXEvalPattern<(and v4i32:$vA, (vnot (and v4i32:$vB, v4i32:$vC))), 14>; + def : Pat<(v4i32 (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), + XXEvalPattern.Instr>; + def : Pat<(v4i32 (and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))), + XXEvalPattern.Instr>; + def : Pat<(v4i32 (and v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), + XXEvalPattern.Instr>; + def : Pat<(v4i32 (and v4i32:$vA, (vnot (or v4i32:$vB, v4i32:$vC)))), + XXEvalPattern.Instr>; + def : Pat<(v4i32 (and v4i32:$vA, (vnot (xor v4i32:$vB, v4i32:$vC)))), + XXEvalPattern.Instr>; + def : Pat<(v4i32 (and v4i32:$vA, (vnot (and v4i32:$vB, v4i32:$vC)))), + XXEvalPattern.Instr>; // NAND // nand(A, B, C) - def : XXEvalPattern<(vnot (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), - !sub(255, 1)>; - // nand(A, xor(B, C)) - def : XXEvalPattern<(vnot (and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))), - !sub(255, 6)>; - // nand(A, or(B, C)) - def : XXEvalPattern<(vnot (and v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), - !sub(255, 7)>; - // nand(A, nor(B, C)) - def : XXEvalPattern<(or (vnot v4i32:$vA), (or v4i32:$vB, v4i32:$vC)), - !sub(255, 8)>; - // nand(A, eqv(B, C)) - def : XXEvalPattern<(or (vnot v4i32:$vA), (xor v4i32:$vB, v4i32:$vC)), - !sub(255, 9)>; - // nand(A, nand(B, C)) - def : XXEvalPattern<(or (vnot v4i32:$vA), (and v4i32:$vB, v4i32:$vC)), - !sub(255, 14)>; + def : Pat<(v4i32 (vnot (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)))), + XXEvalPattern.Instr>; + def : Pat<(v4i32 (vnot (and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)))), + XXEvalPattern.Instr>; + def : Pat<(v4i32 (vnot (and v4i32:$vA, (or v4i32:$vB, v4i32:$vC)))), + XXEvalPattern.Instr>; + def : Pat<(v4i32 (or (vnot v4i32:$vA), (or v4i32:$vB, v4i32:$vC))), + XXEvalPattern.Instr>; + def : Pat<(v4i32 (or (vnot v4i32:$vA), (xor v4i32:$vB, v4i32:$vC))), + XXEvalPattern.Instr>; + def : Pat<(v4i32 (or (vnot v4i32:$vA), (and v4i32:$vB, v4i32:$vC))), + XXEvalPattern.Instr>; // EQV // (eqv A, B, C) - def : XXEvalPattern<(or (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), - (vnot (or v4i32:$vA, (or v4i32:$vB, v4i32:$vC)))), - 150>; - // (eqv A, (and B, C)) - def : XXEvalPattern<(vnot (xor v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), 225>; - // (eqv A, (or B, C)) - def : XXEvalPattern<(vnot (xor v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), 135>; + def : Pat<(v4i32 (or (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), + (vnot (or v4i32:$vA, (or v4i32:$vB, v4i32:$vC))))), + XXEvalPattern.Instr>; + def : Pat<(v4i32 (vnot (xor v4i32:$vA, (and v4i32:$vB, v4i32:$vC)))), + XXEvalPattern.Instr>; + def : Pat<(v4i32 (vnot (xor v4i32:$vA, (or v4i32:$vB, v4i32:$vC)))), + XXEvalPattern.Instr>; // NOR // (nor A, B, C) - def : XXEvalPattern<(vnot (or v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), 128>; - // (nor A, (and B, C)) - def : XXEvalPattern<(vnot (or v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), 224>; - // (nor A, (eqv B, C)) - def : XXEvalPattern<(and (vnot v4i32:$vA), (xor v4i32:$vB, v4i32:$vC)), 96>; - // (nor A, (nand B, C)) - def : XXEvalPattern<(and (vnot v4i32:$vA), (and v4i32:$vB, v4i32:$vC)), 16>; - // (nor A, (nor B, C)) - def : XXEvalPattern<(and (vnot v4i32:$vA), (or v4i32:$vB, v4i32:$vC)), 112>; - // (nor A, (xor B, C)) - def : XXEvalPattern<(vnot (or v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))), 144>; + def : Pat<(v4i32 (vnot (or v4i32:$vA, (or v4i32:$vB, v4i32:$vC)))), + XXEvalPattern.Instr>; + def : Pat<(v4i32 (vnot (or v4i32:$vA, (and v4i32:$vB, v4i32:$vC)))), + XXEvalPattern.Instr>; + def : Pat<(v4i32 (and (vnot v4i32:$vA), (xor v4i32:$vB, v4i32:$vC))), + XXEvalPattern.Instr>; + def : Pat<(v4i32 (and (vnot v4i32:$vA), (and v4i32:$vB, v4i32:$vC))), + XXEvalPattern.Instr>; + def : Pat<(v4i32 (and (vnot v4i32:$vA), (or v4i32:$vB, v4i32:$vC))), + XXEvalPattern.Instr>; + def : Pat<(v4i32 (vnot (or v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)))), + XXEvalPattern.Instr>; // OR // (or A, B, C) - def : XXEvalPattern<(or v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 127>; - // (or A, (and B, C)) - def : XXEvalPattern<(or v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 31>; - // (or A, (eqv B, C)) - def : XXEvalPattern<(or v4i32:$vA, (vnot (xor v4i32:$vB, v4i32:$vC))), 159>; - // (or A, (nand B, C)) - def : XXEvalPattern<(or v4i32:$vA, (vnot (and v4i32:$vB, v4i32:$vC))), 239>; - // (or A, (nor B, C)) - def : XXEvalPattern<(or v4i32:$vA, (vnot (or v4i32:$vB, v4i32:$vC))), 143>; - // (or A, (xor B, C)) - def : XXEvalPattern<(or v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 111>; + def : Pat<(v4i32 (or v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), + XXEvalPattern.Instr>; + def : Pat<(v4i32 (or v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), + XXEvalPattern.Instr>; + def : Pat<(v4i32 (or v4i32:$vA, (vnot (xor v4i32:$vB, v4i32:$vC)))), + XXEvalPattern.Instr>; + def : Pat<(v4i32 (or v4i32:$vA, (vnot (and v4i32:$vB, v4i32:$vC)))), + XXEvalPattern.Instr>; + def : Pat<(v4i32 (or v4i32:$vA, (vnot (or v4i32:$vB, v4i32:$vC)))), + XXEvalPattern.Instr>; + def : Pat<(v4i32 (or v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))), + XXEvalPattern.Instr>; // XOR // (xor A, B, C) - def : XXEvalPattern<(xor v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 105>; - // (xor A, (and B, C)) - def : XXEvalPattern<(xor v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 30>; - // (xor A, (or B, C)) - def : XXEvalPattern<(xor v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 120>; + def : Pat<(v4i32 (xor v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))), + XXEvalPattern.Instr>; + def : Pat<(v4i32 (xor v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), + XXEvalPattern.Instr>; + def : Pat<(v4i32 (xor v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), + XXEvalPattern.Instr>; + + // Add XXEval Patterns for ternary Operations. + // For VSRC-native types (direct XXEVAL support) + foreach Ty = [v4i32, v2i64, v8i16, v16i8] in { + defm : XXEvalXAnd; + } // Anonymous patterns to select prefixed VSX loads and stores. // Load / Store f128 diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll index 57d4c48a1aaa2..b41220b01373a 100644 --- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll +++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; Test file to verify the emission of Vector Selection instructions when ternary operators are used. +; Test file to verify the emission of Vector Evaluate instructions when ternary operators are used. ; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \ ; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s @@ -15,11 +15,9 @@ define <4 x i32> @ternary_A_xor_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i ; CHECK-LABEL: ternary_A_xor_BC_and_BC_4x32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxleqv v5, v5, v5 -; CHECK-NEXT: xxlxor vs0, v3, v4 -; CHECK-NEXT: xxland vs1, v3, v4 ; CHECK-NEXT: vslw v2, v2, v5 ; CHECK-NEXT: vsraw v2, v2, v5 -; CHECK-NEXT: xxsel v2, vs1, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 22 ; CHECK-NEXT: blr entry: %xor = xor <4 x i32> %B, %C @@ -33,12 +31,10 @@ define <2 x i64> @ternary_A_xor_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i ; CHECK-LABEL: ternary_A_xor_BC_and_BC_2x64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxlxor v5, v5, v5 -; CHECK-NEXT: xxlxor vs0, v3, v4 -; CHECK-NEXT: xxland vs1, v3, v4 ; CHECK-NEXT: xxsplti32dx v5, 1, 63 ; CHECK-NEXT: vsld v2, v2, v5 ; CHECK-NEXT: vsrad v2, v2, v5 -; CHECK-NEXT: xxsel v2, vs1, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 22 ; CHECK-NEXT: blr entry: %xor = xor <2 x i64> %B, %C @@ -52,11 +48,9 @@ define <16 x i8> @ternary_A_xor_BC_and_BC_16x8(<16 x i1> %A, <16 x i8> %B, <16 x ; CHECK-LABEL: ternary_A_xor_BC_and_BC_16x8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxspltib v5, 7 -; CHECK-NEXT: xxlxor vs0, v3, v4 -; CHECK-NEXT: xxland vs1, v3, v4 ; CHECK-NEXT: vslb v2, v2, v5 ; CHECK-NEXT: vsrab v2, v2, v5 -; CHECK-NEXT: xxsel v2, vs1, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 22 ; CHECK-NEXT: blr entry: %xor = xor <16 x i8> %B, %C @@ -70,11 +64,9 @@ define <8 x i16> @ternary_A_xor_BC_and_BC_8x16(<8 x i1> %A, <8 x i16> %B, <8 x i ; CHECK-LABEL: ternary_A_xor_BC_and_BC_8x16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxspltiw v5, 983055 -; CHECK-NEXT: xxlxor vs0, v3, v4 -; CHECK-NEXT: xxland vs1, v3, v4 ; CHECK-NEXT: vslh v2, v2, v5 ; CHECK-NEXT: vsrah v2, v2, v5 -; CHECK-NEXT: xxsel v2, vs1, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 22 ; CHECK-NEXT: blr entry: %xor = xor <8 x i16> %B, %C @@ -88,11 +80,9 @@ define <4 x i32> @ternary_A_nor_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i ; CHECK-LABEL: ternary_A_nor_BC_and_BC_4x32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxleqv v5, v5, v5 -; CHECK-NEXT: xxlnor vs0, v3, v4 -; CHECK-NEXT: xxland vs1, v3, v4 ; CHECK-NEXT: vslw v2, v2, v5 ; CHECK-NEXT: vsraw v2, v2, v5 -; CHECK-NEXT: xxsel v2, vs1, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 24 ; CHECK-NEXT: blr entry: %or = or <4 x i32> %B, %C @@ -107,12 +97,10 @@ define <2 x i64> @ternary_A_nor_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i ; CHECK-LABEL: ternary_A_nor_BC_and_BC_2x64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxlxor v5, v5, v5 -; CHECK-NEXT: xxlnor vs0, v3, v4 -; CHECK-NEXT: xxland vs1, v3, v4 ; CHECK-NEXT: xxsplti32dx v5, 1, 63 ; CHECK-NEXT: vsld v2, v2, v5 ; CHECK-NEXT: vsrad v2, v2, v5 -; CHECK-NEXT: xxsel v2, vs1, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 24 ; CHECK-NEXT: blr entry: %or = or <2 x i64> %B, %C @@ -127,11 +115,9 @@ define <16 x i8> @ternary_A_nor_BC_and_BC_16x8(<16 x i1> %A, <16 x i8> %B, <16 x ; CHECK-LABEL: ternary_A_nor_BC_and_BC_16x8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxspltib v5, 7 -; CHECK-NEXT: xxlnor vs0, v3, v4 -; CHECK-NEXT: xxland vs1, v3, v4 ; CHECK-NEXT: vslb v2, v2, v5 ; CHECK-NEXT: vsrab v2, v2, v5 -; CHECK-NEXT: xxsel v2, vs1, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 24 ; CHECK-NEXT: blr entry: %or = or <16 x i8> %B, %C @@ -146,11 +132,9 @@ define <8 x i16> @ternary_A_nor_BC_and_BC_8x16(<8 x i1> %A, <8 x i16> %B, <8 x i ; CHECK-LABEL: ternary_A_nor_BC_and_BC_8x16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxspltiw v5, 983055 -; CHECK-NEXT: xxlnor vs0, v3, v4 -; CHECK-NEXT: xxland vs1, v3, v4 ; CHECK-NEXT: vslh v2, v2, v5 ; CHECK-NEXT: vsrah v2, v2, v5 -; CHECK-NEXT: xxsel v2, vs1, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 24 ; CHECK-NEXT: blr entry: %or = or <8 x i16> %B, %C @@ -165,11 +149,9 @@ define <4 x i32> @ternary_A_eqv_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i ; CHECK-LABEL: ternary_A_eqv_BC_and_BC_4x32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxleqv v5, v5, v5 -; CHECK-NEXT: xxleqv vs0, v3, v4 -; CHECK-NEXT: xxland vs1, v3, v4 ; CHECK-NEXT: vslw v2, v2, v5 ; CHECK-NEXT: vsraw v2, v2, v5 -; CHECK-NEXT: xxsel v2, vs1, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 25 ; CHECK-NEXT: blr entry: %xor = xor <4 x i32> %B, %C @@ -184,12 +166,10 @@ define <2 x i64> @ternary_A_eqv_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i ; CHECK-LABEL: ternary_A_eqv_BC_and_BC_2x64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxlxor v5, v5, v5 -; CHECK-NEXT: xxleqv vs0, v3, v4 -; CHECK-NEXT: xxland vs1, v3, v4 ; CHECK-NEXT: xxsplti32dx v5, 1, 63 ; CHECK-NEXT: vsld v2, v2, v5 ; CHECK-NEXT: vsrad v2, v2, v5 -; CHECK-NEXT: xxsel v2, vs1, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 25 ; CHECK-NEXT: blr entry: %xor = xor <2 x i64> %B, %C @@ -204,11 +184,9 @@ define <16 x i8> @ternary_A_eqv_BC_and_BC_16x8(<16 x i1> %A, <16 x i8> %B, <16 x ; CHECK-LABEL: ternary_A_eqv_BC_and_BC_16x8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxspltib v5, 7 -; CHECK-NEXT: xxleqv vs0, v3, v4 -; CHECK-NEXT: xxland vs1, v3, v4 ; CHECK-NEXT: vslb v2, v2, v5 ; CHECK-NEXT: vsrab v2, v2, v5 -; CHECK-NEXT: xxsel v2, vs1, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 25 ; CHECK-NEXT: blr entry: %xor = xor <16 x i8> %B, %C @@ -223,11 +201,9 @@ define <8 x i16> @ternary_A_eqv_BC_and_BC_8x16(<8 x i1> %A, <8 x i16> %B, <8 x i ; CHECK-LABEL: ternary_A_eqv_BC_and_BC_8x16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxspltiw v5, 983055 -; CHECK-NEXT: xxleqv vs0, v3, v4 -; CHECK-NEXT: xxland vs1, v3, v4 ; CHECK-NEXT: vslh v2, v2, v5 ; CHECK-NEXT: vsrah v2, v2, v5 -; CHECK-NEXT: xxsel v2, vs1, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 25 ; CHECK-NEXT: blr entry: %xor = xor <8 x i16> %B, %C @@ -242,11 +218,9 @@ define <4 x i32> @ternary_A_not_C_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i3 ; CHECK-LABEL: ternary_A_not_C_and_BC_4x32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxleqv v5, v5, v5 -; CHECK-NEXT: xxlnor vs0, v4, v4 -; CHECK-NEXT: xxland vs1, v3, v4 ; CHECK-NEXT: vslw v2, v2, v5 ; CHECK-NEXT: vsraw v2, v2, v5 -; CHECK-NEXT: xxsel v2, vs1, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 26 ; CHECK-NEXT: blr entry: %not = xor <4 x i32> %C, ; Vector not operation @@ -260,12 +234,10 @@ define <2 x i64> @ternary_A_not_C_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i6 ; CHECK-LABEL: ternary_A_not_C_and_BC_2x64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxlxor v5, v5, v5 -; CHECK-NEXT: xxlnor vs0, v4, v4 -; CHECK-NEXT: xxland vs1, v3, v4 ; CHECK-NEXT: xxsplti32dx v5, 1, 63 ; CHECK-NEXT: vsld v2, v2, v5 ; CHECK-NEXT: vsrad v2, v2, v5 -; CHECK-NEXT: xxsel v2, vs1, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 26 ; CHECK-NEXT: blr entry: %not = xor <2 x i64> %C, ; Vector not operation @@ -279,11 +251,9 @@ define <16 x i8> @ternary_A_not_C_and_BC_16x8(<16 x i1> %A, <16 x i8> %B, <16 x ; CHECK-LABEL: ternary_A_not_C_and_BC_16x8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxspltib v5, 7 -; CHECK-NEXT: xxlnor vs0, v4, v4 -; CHECK-NEXT: xxland vs1, v3, v4 ; CHECK-NEXT: vslb v2, v2, v5 ; CHECK-NEXT: vsrab v2, v2, v5 -; CHECK-NEXT: xxsel v2, vs1, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 26 ; CHECK-NEXT: blr entry: %not = xor <16 x i8> %C, ; Vector not operation @@ -297,11 +267,9 @@ define <8 x i16> @ternary_A_not_C_and_BC_8x16(<8 x i1> %A, <8 x i16> %B, <8 x i1 ; CHECK-LABEL: ternary_A_not_C_and_BC_8x16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxspltiw v5, 983055 -; CHECK-NEXT: xxlnor vs0, v4, v4 -; CHECK-NEXT: xxland vs1, v3, v4 ; CHECK-NEXT: vslh v2, v2, v5 ; CHECK-NEXT: vsrah v2, v2, v5 -; CHECK-NEXT: xxsel v2, vs1, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 26 ; CHECK-NEXT: blr entry: %not = xor <8 x i16> %C, ; Vector not operation @@ -315,11 +283,9 @@ define <4 x i32> @ternary_A_not_B_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i3 ; CHECK-LABEL: ternary_A_not_B_and_BC_4x32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxleqv v5, v5, v5 -; CHECK-NEXT: xxlnor vs0, v3, v3 -; CHECK-NEXT: xxland vs1, v3, v4 ; CHECK-NEXT: vslw v2, v2, v5 ; CHECK-NEXT: vsraw v2, v2, v5 -; CHECK-NEXT: xxsel v2, vs1, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 28 ; CHECK-NEXT: blr entry: %not = xor <4 x i32> %B, ; Vector not operation @@ -333,12 +299,10 @@ define <2 x i64> @ternary_A_not_B_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i6 ; CHECK-LABEL: ternary_A_not_B_and_BC_2x64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxlxor v5, v5, v5 -; CHECK-NEXT: xxlnor vs0, v3, v3 -; CHECK-NEXT: xxland vs1, v3, v4 ; CHECK-NEXT: xxsplti32dx v5, 1, 63 ; CHECK-NEXT: vsld v2, v2, v5 ; CHECK-NEXT: vsrad v2, v2, v5 -; CHECK-NEXT: xxsel v2, vs1, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 28 ; CHECK-NEXT: blr entry: %not = xor <2 x i64> %B, ; Vector not operation @@ -352,11 +316,9 @@ define <16 x i8> @ternary_A_not_B_and_BC_16x8(<16 x i1> %A, <16 x i8> %B, <16 x ; CHECK-LABEL: ternary_A_not_B_and_BC_16x8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxspltib v5, 7 -; CHECK-NEXT: xxlnor vs0, v3, v3 -; CHECK-NEXT: xxland vs1, v3, v4 ; CHECK-NEXT: vslb v2, v2, v5 ; CHECK-NEXT: vsrab v2, v2, v5 -; CHECK-NEXT: xxsel v2, vs1, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 28 ; CHECK-NEXT: blr entry: %not = xor <16 x i8> %B, ; Vector not operation @@ -370,11 +332,9 @@ define <8 x i16> @ternary_A_not_B_and_BC_8x16(<8 x i1> %A, <8 x i16> %B, <8 x i1 ; CHECK-LABEL: ternary_A_not_B_and_BC_8x16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxspltiw v5, 983055 -; CHECK-NEXT: xxlnor vs0, v3, v3 -; CHECK-NEXT: xxland vs1, v3, v4 ; CHECK-NEXT: vslh v2, v2, v5 ; CHECK-NEXT: vsrah v2, v2, v5 -; CHECK-NEXT: xxsel v2, vs1, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 28 ; CHECK-NEXT: blr entry: %not = xor <8 x i16> %B, ; Vector not operation