From 845a9c7434daa8268b0715aa5e28b8cc287e7dfb Mon Sep 17 00:00:00 2001 From: Sjoerd Meijer Date: Wed, 21 May 2025 05:47:44 -0700 Subject: [PATCH] [AArch64] Neoverse V2 FeatureDisableLatencySchedHeuristic This adds FeatureDisableLatencySchedHeuristic to the Neoverse V2 core tuning description. This gives us a 20% improvement on a key workload, some other minor improvements here and there, and no real regressions; nothing outside the noise levels. Earlier attempts to solve this problems included disabling the MI scheduler entirely (#127784), and #139557 was about a heuristic to not schedule hand-written vector code. This solution is preferred because it avoids another heuristic and achieves what we want, and for what is worth, there is a lot of precedent for setting this feature. Thanks to: - Ricardo Jesus for pointing out this subtarget feature, and - Cameron McInally for the extensive performance testing. --- llvm/lib/Target/AArch64/AArch64Processors.td | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td index a5f0f6a2eb150..e7a3527202f6a 100644 --- a/llvm/lib/Target/AArch64/AArch64Processors.td +++ b/llvm/lib/Target/AArch64/AArch64Processors.td @@ -561,7 +561,8 @@ def TuneNeoverseV2 : SubtargetFeature<"neoversev2", "ARMProcFamily", "NeoverseV2 FeatureEnableSelectOptimize, FeatureUseFixedOverScalableIfEqualCost, FeatureAvoidLDAPUR, - FeaturePredictableSelectIsExpensive]>; + FeaturePredictableSelectIsExpensive, + FeatureDisableLatencySchedHeuristic]>; def TuneNeoverseV3 : SubtargetFeature<"neoversev3", "ARMProcFamily", "NeoverseV3", "Neoverse V3 ARM processors", [