From 7e531fdf14cbaccb396647360793e8517d169588 Mon Sep 17 00:00:00 2001 From: Yingwei Zheng Date: Wed, 23 Apr 2025 19:30:22 +0800 Subject: [PATCH 1/2] [InstCombine] Add pre-commit tests. NFC. --- llvm/test/Transforms/InstCombine/and-fcmp.ll | 26 ++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/llvm/test/Transforms/InstCombine/and-fcmp.ll b/llvm/test/Transforms/InstCombine/and-fcmp.ll index c7bbc8ab56f9a..058455a1a83d7 100644 --- a/llvm/test/Transforms/InstCombine/and-fcmp.ll +++ b/llvm/test/Transforms/InstCombine/and-fcmp.ll @@ -4990,6 +4990,32 @@ define i1 @clang_builtin_isnormal_inf_check_copysign(half %x, half %y) { ret i1 %and } +define i1 @clang_builtin_isnormal_inf_check_copysign_logical_select(half %x, half %y) { +; CHECK-LABEL: @clang_builtin_isnormal_inf_check_copysign_logical_select( +; CHECK-NEXT: [[COPYSIGN_X:%.*]] = call half @llvm.copysign.f16(half [[X:%.*]], half [[Y:%.*]]) +; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[COPYSIGN_X]], 0xH7C00 +; CHECK-NEXT: ret i1 [[AND]] +; + %copysign.x = call half @llvm.copysign.f16(half %x, half %y) + %ord = fcmp ord half %x, 0.0 + %cmp = fcmp uge half %copysign.x, 0xH7C00 + %and = select i1 %ord, i1 %cmp, i1 false + ret i1 %and +} + +define i1 @clang_builtin_isnormal_inf_check_fabs_nnan_logical_select(half %x) { +; CHECK-LABEL: @clang_builtin_isnormal_inf_check_fabs_nnan_logical_select( +; CHECK-NEXT: [[COPYSIGN_X:%.*]] = call nnan half @llvm.fabs.f16(half [[X:%.*]]) +; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[COPYSIGN_X]], 0xH7C00 +; CHECK-NEXT: ret i1 [[AND]] +; + %copysign.x = call nnan half @llvm.fabs.f16(half %x) + %ord = fcmp ord half %x, 0.0 + %cmp = fcmp uge half %copysign.x, 0xH7C00 + %and = select i1 %ord, i1 %cmp, i1 false + ret i1 %and +} + define i1 @isnormal_logical_select_0(half %x) { ; CHECK-LABEL: @isnormal_logical_select_0( ; CHECK-NEXT: [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]]) From 7cb989a6dd880f3ff121504b27ccba08a406db23 Mon Sep 17 00:00:00 2001 From: Yingwei Zheng Date: Wed, 23 Apr 2025 19:36:04 +0800 Subject: [PATCH 2/2] [InstCombine] Do not fold logical is_finite test --- llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp | 4 +++- llvm/test/Transforms/InstCombine/and-fcmp.ll | 6 ++++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp index f1b225c0f238a..979a9cbedf2ef 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp @@ -1480,7 +1480,9 @@ Value *InstCombinerImpl::foldLogicOfFCmps(FCmpInst *LHS, FCmpInst *RHS, } } - if (IsAnd && stripSignOnlyFPOps(LHS0) == stripSignOnlyFPOps(RHS0)) { + // This transform is not valid for a logical select. + if (!IsLogicalSelect && IsAnd && + stripSignOnlyFPOps(LHS0) == stripSignOnlyFPOps(RHS0)) { // and (fcmp ord x, 0), (fcmp u* x, inf) -> fcmp o* x, inf // and (fcmp ord x, 0), (fcmp u* fabs(x), inf) -> fcmp o* x, inf if (Value *Left = matchIsFiniteTest(Builder, LHS, RHS)) diff --git a/llvm/test/Transforms/InstCombine/and-fcmp.ll b/llvm/test/Transforms/InstCombine/and-fcmp.ll index 058455a1a83d7..ec1b6ad2ea168 100644 --- a/llvm/test/Transforms/InstCombine/and-fcmp.ll +++ b/llvm/test/Transforms/InstCombine/and-fcmp.ll @@ -4993,7 +4993,9 @@ define i1 @clang_builtin_isnormal_inf_check_copysign(half %x, half %y) { define i1 @clang_builtin_isnormal_inf_check_copysign_logical_select(half %x, half %y) { ; CHECK-LABEL: @clang_builtin_isnormal_inf_check_copysign_logical_select( ; CHECK-NEXT: [[COPYSIGN_X:%.*]] = call half @llvm.copysign.f16(half [[X:%.*]], half [[Y:%.*]]) -; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[COPYSIGN_X]], 0xH7C00 +; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000 +; CHECK-NEXT: [[CMP:%.*]] = fcmp ueq half [[COPYSIGN_X]], 0xH7C00 +; CHECK-NEXT: [[AND:%.*]] = select i1 [[ORD]], i1 [[CMP]], i1 false ; CHECK-NEXT: ret i1 [[AND]] ; %copysign.x = call half @llvm.copysign.f16(half %x, half %y) @@ -5005,7 +5007,7 @@ define i1 @clang_builtin_isnormal_inf_check_copysign_logical_select(half %x, hal define i1 @clang_builtin_isnormal_inf_check_fabs_nnan_logical_select(half %x) { ; CHECK-LABEL: @clang_builtin_isnormal_inf_check_fabs_nnan_logical_select( -; CHECK-NEXT: [[COPYSIGN_X:%.*]] = call nnan half @llvm.fabs.f16(half [[X:%.*]]) +; CHECK-NEXT: [[COPYSIGN_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]]) ; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[COPYSIGN_X]], 0xH7C00 ; CHECK-NEXT: ret i1 [[AND]] ;