From 4af902ce9d70df048bc15888fa14339aa91d8ef4 Mon Sep 17 00:00:00 2001 From: Robert Imschweiler Date: Mon, 24 Mar 2025 05:51:23 -0500 Subject: [PATCH 1/2] [AMDGPU] Fix handling of FP in cs.chain functions In case there is an dynamic alloca / an alloca which is not in the entry block, cs.chain functions don't setup an FP, but are reported to need one. This results in a failed assertion in `SIFrameLowering::emitPrologue()` (Assertion `(!HasFP || FPSaved) && "Needed to save FP but didn't save it anywhere"' failed.) This commit changes `hasFPImpl` so that the need for an SP in a cs.chain function does not directly imply the need for an FP anymore. This LLVM defect was identified via the AMD Fuzzing project. --- llvm/lib/Target/AMDGPU/SIFrameLowering.cpp | 4 +- .../AMDGPU/amdgpu-cs-chain-fp-nosave.ll | 78 +++++++++++++++++++ 2 files changed, 81 insertions(+), 1 deletion(-) create mode 100644 llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp index 97736e2410c18..9bbb6c9c47ff3 100644 --- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp @@ -1828,7 +1828,9 @@ bool SIFrameLowering::hasFPImpl(const MachineFunction &MF) const { return MFI.getStackSize() != 0; } - return frameTriviallyRequiresSP(MFI) || MFI.isFrameAddressTaken() || + return (frameTriviallyRequiresSP(MFI) && + !MF.getInfo()->isChainFunction()) || + MFI.isFrameAddressTaken() || MF.getSubtarget().getRegisterInfo()->hasStackRealignment( MF) || MF.getTarget().Options.DisableFramePointerElim(MF); diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll new file mode 100644 index 0000000000000..8b7ec78197fd3 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll @@ -0,0 +1,78 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple=amdgcn -mcpu=gfx942 -o - < %s 2>&1 | FileCheck %s + +; These situations are "special" in that they have an alloca not in the entry +; block, which affects prolog/epilog generation. + +declare amdgpu_gfx void @foo() + +define amdgpu_cs_chain void @test_alloca() { +; CHECK-LABEL: test_alloca: +; CHECK: ; %bb.0: ; %.entry +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_mov_b32 s32, 16 +; CHECK-NEXT: s_mov_b32 s0, s32 +; CHECK-NEXT: v_mov_b32_e32 v0, 0 +; CHECK-NEXT: s_add_i32 s32, s0, 0x400 +; CHECK-NEXT: scratch_store_dword off, v0, s0 +; CHECK-NEXT: s_endpgm +.entry: + br label %SW_C + +SW_C: ; preds = %.entry + %v = alloca i32, i32 1, align 4, addrspace(5) + store i32 0, ptr addrspace(5) %v, align 4 + ret void +} + +define amdgpu_cs_chain void @test_alloca_and_call() { +; CHECK-LABEL: test_alloca_and_call: +; CHECK: ; %bb.0: ; %.entry +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_getpc_b64 s[0:1] +; CHECK-NEXT: s_add_u32 s0, s0, foo@gotpcrel32@lo+4 +; CHECK-NEXT: s_addc_u32 s1, s1, foo@gotpcrel32@hi+12 +; CHECK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 +; CHECK-NEXT: s_mov_b32 s32, 16 +; CHECK-NEXT: s_mov_b32 s2, s32 +; CHECK-NEXT: v_mov_b32_e32 v0, 0 +; CHECK-NEXT: s_add_i32 s32, s2, 0x400 +; CHECK-NEXT: scratch_store_dword off, v0, s2 +; CHECK-NEXT: s_waitcnt lgkmcnt(0) +; CHECK-NEXT: s_swappc_b64 s[30:31], s[0:1] +; CHECK-NEXT: s_endpgm +.entry: + br label %SW_C + +SW_C: ; preds = %.entry + %v = alloca i32, i32 1, align 4, addrspace(5) + store i32 0, ptr addrspace(5) %v, align 4 + call amdgpu_gfx void @foo() + ret void +} + +define amdgpu_cs_chain void @test_call_and_alloca() { +; CHECK-LABEL: test_call_and_alloca: +; CHECK: ; %bb.0: ; %.entry +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_getpc_b64 s[0:1] +; CHECK-NEXT: s_add_u32 s0, s0, foo@gotpcrel32@lo+4 +; CHECK-NEXT: s_addc_u32 s1, s1, foo@gotpcrel32@hi+12 +; CHECK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 +; CHECK-NEXT: s_mov_b32 s32, 16 +; CHECK-NEXT: s_mov_b32 s4, s32 +; CHECK-NEXT: s_add_i32 s32, s4, 0x400 +; CHECK-NEXT: s_waitcnt lgkmcnt(0) +; CHECK-NEXT: s_swappc_b64 s[30:31], s[0:1] +; CHECK-NEXT: v_mov_b32_e32 v0, 0 +; CHECK-NEXT: scratch_store_dword off, v0, s4 +; CHECK-NEXT: s_endpgm +.entry: + br label %SW_C + +SW_C: ; preds = %.entry + %v = alloca i32, i32 1, align 4, addrspace(5) + call amdgpu_gfx void @foo() + store i32 0, ptr addrspace(5) %v, align 4 + ret void +} From c55f05e6d644a02e284f7662ccb257215df54e70 Mon Sep 17 00:00:00 2001 From: Robert Imschweiler Date: Mon, 24 Mar 2025 10:51:00 -0500 Subject: [PATCH 2/2] change target to gfx12 --- .../AMDGPU/amdgpu-cs-chain-fp-nosave.ll | 65 +++++++++++++------ 1 file changed, 45 insertions(+), 20 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll index 8b7ec78197fd3..2979c1d867670 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn -mcpu=gfx942 -o - < %s 2>&1 | FileCheck %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -o - < %s 2>&1 | FileCheck %s ; These situations are "special" in that they have an alloca not in the entry ; block, which affects prolog/epilog generation. @@ -9,12 +9,18 @@ declare amdgpu_gfx void @foo() define amdgpu_cs_chain void @test_alloca() { ; CHECK-LABEL: test_alloca: ; CHECK: ; %bb.0: ; %.entry -; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0 +; CHECK-NEXT: s_wait_expcnt 0x0 +; CHECK-NEXT: s_wait_samplecnt 0x0 +; CHECK-NEXT: s_wait_bvhcnt 0x0 +; CHECK-NEXT: s_wait_kmcnt 0x0 +; CHECK-NEXT: v_mov_b32_e32 v0, 0 ; CHECK-NEXT: s_mov_b32 s32, 16 +; CHECK-NEXT: s_wait_alu 0xfffe ; CHECK-NEXT: s_mov_b32 s0, s32 -; CHECK-NEXT: v_mov_b32_e32 v0, 0 -; CHECK-NEXT: s_add_i32 s32, s0, 0x400 -; CHECK-NEXT: scratch_store_dword off, v0, s0 +; CHECK-NEXT: s_wait_alu 0xfffe +; CHECK-NEXT: s_add_co_i32 s32, s0, 0x200 +; CHECK-NEXT: scratch_store_b32 off, v0, s0 ; CHECK-NEXT: s_endpgm .entry: br label %SW_C @@ -28,17 +34,27 @@ SW_C: ; preds = %.entry define amdgpu_cs_chain void @test_alloca_and_call() { ; CHECK-LABEL: test_alloca_and_call: ; CHECK: ; %bb.0: ; %.entry -; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0 +; CHECK-NEXT: s_wait_expcnt 0x0 +; CHECK-NEXT: s_wait_samplecnt 0x0 +; CHECK-NEXT: s_wait_bvhcnt 0x0 +; CHECK-NEXT: s_wait_kmcnt 0x0 ; CHECK-NEXT: s_getpc_b64 s[0:1] -; CHECK-NEXT: s_add_u32 s0, s0, foo@gotpcrel32@lo+4 -; CHECK-NEXT: s_addc_u32 s1, s1, foo@gotpcrel32@hi+12 -; CHECK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 +; CHECK-NEXT: s_wait_alu 0xfffe +; CHECK-NEXT: s_sext_i32_i16 s1, s1 +; CHECK-NEXT: s_add_co_u32 s0, s0, foo@gotpcrel32@lo+12 +; CHECK-NEXT: s_wait_alu 0xfffe +; CHECK-NEXT: s_add_co_ci_u32 s1, s1, foo@gotpcrel32@hi+24 +; CHECK-NEXT: v_mov_b32_e32 v0, 0 +; CHECK-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; CHECK-NEXT: s_mov_b32 s32, 16 +; CHECK-NEXT: s_wait_alu 0xfffe ; CHECK-NEXT: s_mov_b32 s2, s32 -; CHECK-NEXT: v_mov_b32_e32 v0, 0 -; CHECK-NEXT: s_add_i32 s32, s2, 0x400 -; CHECK-NEXT: scratch_store_dword off, v0, s2 -; CHECK-NEXT: s_waitcnt lgkmcnt(0) +; CHECK-NEXT: s_wait_alu 0xfffe +; CHECK-NEXT: s_add_co_i32 s32, s2, 0x200 +; CHECK-NEXT: scratch_store_b32 off, v0, s2 +; CHECK-NEXT: s_wait_kmcnt 0x0 +; CHECK-NEXT: s_wait_alu 0xfffe ; CHECK-NEXT: s_swappc_b64 s[30:31], s[0:1] ; CHECK-NEXT: s_endpgm .entry: @@ -54,18 +70,27 @@ SW_C: ; preds = %.entry define amdgpu_cs_chain void @test_call_and_alloca() { ; CHECK-LABEL: test_call_and_alloca: ; CHECK: ; %bb.0: ; %.entry -; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0 +; CHECK-NEXT: s_wait_expcnt 0x0 +; CHECK-NEXT: s_wait_samplecnt 0x0 +; CHECK-NEXT: s_wait_bvhcnt 0x0 +; CHECK-NEXT: s_wait_kmcnt 0x0 ; CHECK-NEXT: s_getpc_b64 s[0:1] -; CHECK-NEXT: s_add_u32 s0, s0, foo@gotpcrel32@lo+4 -; CHECK-NEXT: s_addc_u32 s1, s1, foo@gotpcrel32@hi+12 -; CHECK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 +; CHECK-NEXT: s_wait_alu 0xfffe +; CHECK-NEXT: s_sext_i32_i16 s1, s1 +; CHECK-NEXT: s_add_co_u32 s0, s0, foo@gotpcrel32@lo+12 +; CHECK-NEXT: s_wait_alu 0xfffe +; CHECK-NEXT: s_add_co_ci_u32 s1, s1, foo@gotpcrel32@hi+24 ; CHECK-NEXT: s_mov_b32 s32, 16 +; CHECK-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; CHECK-NEXT: s_mov_b32 s4, s32 -; CHECK-NEXT: s_add_i32 s32, s4, 0x400 -; CHECK-NEXT: s_waitcnt lgkmcnt(0) +; CHECK-NEXT: s_wait_alu 0xfffe +; CHECK-NEXT: s_add_co_i32 s32, s4, 0x200 +; CHECK-NEXT: s_wait_kmcnt 0x0 +; CHECK-NEXT: s_wait_alu 0xfffe ; CHECK-NEXT: s_swappc_b64 s[30:31], s[0:1] ; CHECK-NEXT: v_mov_b32_e32 v0, 0 -; CHECK-NEXT: scratch_store_dword off, v0, s4 +; CHECK-NEXT: scratch_store_b32 off, v0, s4 ; CHECK-NEXT: s_endpgm .entry: br label %SW_C