diff --git a/llvm/test/CodeGen/AMDGPU/32-bit-local-address-space.ll b/llvm/test/CodeGen/AMDGPU/32-bit-local-address-space.ll index f257e87dba22e..5e9c75283105c 100644 --- a/llvm/test/CodeGen/AMDGPU/32-bit-local-address-space.ll +++ b/llvm/test/CodeGen/AMDGPU/32-bit-local-address-space.ll @@ -92,7 +92,7 @@ define amdgpu_kernel void @infer_ptr_alignment_global_offset(ptr addrspace(1) %o } -@ptr = addrspace(3) global ptr addrspace(3) undef +@ptr = addrspace(3) global ptr addrspace(3) poison @dst = addrspace(3) global [16383 x i32] undef ; FUNC-LABEL: {{^}}global_ptr: diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll index 137d057ef2df3..31a229a908142 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll @@ -1619,7 +1619,7 @@ define amdgpu_ps void @dyn_extract_v8p3_s_s(<8 x ptr addrspace(3)> inreg %vec, i ; GFX11-NEXT: s_endpgm entry: %ext = extractelement <8 x ptr addrspace(3)> %vec, i32 %idx - store ptr addrspace(3) %ext, ptr addrspace(3) undef + store ptr addrspace(3) %ext, ptr addrspace(3) poison ret void } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmax_legacy.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmax_legacy.ll index 3d5f908c8667f..388cc97643bf7 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmax_legacy.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmax_legacy.ll @@ -229,7 +229,7 @@ define float @v_test_fmax_legacy_ule_f32_multi_use(float %a, float %b) { %cmp = fcmp ogt float %a, %b %val0 = select i1 %cmp, float %a, float %b %val1 = zext i1 %cmp to i32 - store i32 %val1, ptr addrspace(3) undef + store i32 %val1, ptr addrspace(3) poison ret float %val0 } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin_legacy.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin_legacy.ll index 10e6b3f1b47b1..54ef9b8a09402 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin_legacy.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin_legacy.ll @@ -212,7 +212,7 @@ define float @v_test_fmin_legacy_ule_f32_multi_use(float %a, float %b) { %cmp = fcmp ule float %a, %b %val0 = select i1 %cmp, float %a, float %b %val1 = zext i1 %cmp to i32 - store i32 %val1, ptr addrspace(3) undef + store i32 %val1, ptr addrspace(3) poison ret float %val0 } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll index 8d7c48d2c94cc..a5d9c2a16d062 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll @@ -1062,10 +1062,10 @@ define { <3 x i32>, i32 } @v3i32_struct_func_void_wasted_reg() #0 { ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 ; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF - ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3) - ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3) - ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3) - ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3) + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) poison`, addrspace 3) + ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) poison`, addrspace 3) + ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) poison`, addrspace 3) + ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) poison`, addrspace 3) ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<3 x s32>) = G_INSERT_VECTOR_ELT [[DEF1]], [[LOAD]](s32), [[C]](s32) ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<3 x s32>) = G_INSERT_VECTOR_ELT [[IVEC]], [[LOAD1]](s32), [[C1]](s32) ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<3 x s32>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[LOAD2]](s32), [[C2]](s32) @@ -1075,10 +1075,10 @@ define { <3 x i32>, i32 } @v3i32_struct_func_void_wasted_reg() #0 { ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32) ; CHECK-NEXT: $vgpr3 = COPY [[LOAD3]](s32) ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 - %load0 = load volatile i32, ptr addrspace(3) undef - %load1 = load volatile i32, ptr addrspace(3) undef - %load2 = load volatile i32, ptr addrspace(3) undef - %load3 = load volatile i32, ptr addrspace(3) undef + %load0 = load volatile i32, ptr addrspace(3) poison + %load1 = load volatile i32, ptr addrspace(3) poison + %load2 = load volatile i32, ptr addrspace(3) poison + %load3 = load volatile i32, ptr addrspace(3) poison %insert.0 = insertelement <3 x i32> poison, i32 %load0, i32 0 %insert.1 = insertelement <3 x i32> %insert.0, i32 %load1, i32 1 @@ -1097,10 +1097,10 @@ define { <3 x float>, i32 } @v3f32_struct_func_void_wasted_reg() #0 { ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 ; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF - ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3) - ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3) - ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3) - ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3) + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) poison`, addrspace 3) + ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) poison`, addrspace 3) + ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) poison`, addrspace 3) + ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) poison`, addrspace 3) ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<3 x s32>) = G_INSERT_VECTOR_ELT [[DEF1]], [[LOAD]](s32), [[C]](s32) ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<3 x s32>) = G_INSERT_VECTOR_ELT [[IVEC]], [[LOAD1]](s32), [[C1]](s32) ; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<3 x s32>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[LOAD2]](s32), [[C2]](s32) @@ -1110,10 +1110,10 @@ define { <3 x float>, i32 } @v3f32_struct_func_void_wasted_reg() #0 { ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32) ; CHECK-NEXT: $vgpr3 = COPY [[LOAD3]](s32) ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 - %load0 = load volatile float, ptr addrspace(3) undef - %load1 = load volatile float, ptr addrspace(3) undef - %load2 = load volatile float, ptr addrspace(3) undef - %load3 = load volatile i32, ptr addrspace(3) undef + %load0 = load volatile float, ptr addrspace(3) poison + %load1 = load volatile float, ptr addrspace(3) poison + %load2 = load volatile float, ptr addrspace(3) poison + %load3 = load volatile i32, ptr addrspace(3) poison %insert.0 = insertelement <3 x float> poison, float %load0, i32 0 %insert.1 = insertelement <3 x float> %insert.0, float %load1, i32 1 @@ -1137,9 +1137,9 @@ define void @void_func_sret_max_known_zero_bits(ptr addrspace(5) sret(i8) %arg0) ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C]](s32) ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C1]](s32) ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C2]](s32) - ; CHECK-NEXT: G_STORE [[LSHR]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3) - ; CHECK-NEXT: G_STORE [[LSHR1]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3) - ; CHECK-NEXT: G_STORE [[LSHR2]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3) + ; CHECK-NEXT: G_STORE [[LSHR]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3) + ; CHECK-NEXT: G_STORE [[LSHR1]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3) + ; CHECK-NEXT: G_STORE [[LSHR2]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3) ; CHECK-NEXT: SI_RETURN %arg0.int = ptrtoint ptr addrspace(5) %arg0 to i32 @@ -1147,9 +1147,9 @@ define void @void_func_sret_max_known_zero_bits(ptr addrspace(5) sret(i8) %arg0) %lshr1 = lshr i32 %arg0.int, 17 %lshr2 = lshr i32 %arg0.int, 18 - store volatile i32 %lshr0, ptr addrspace(3) undef - store volatile i32 %lshr1, ptr addrspace(3) undef - store volatile i32 %lshr2, ptr addrspace(3) undef + store volatile i32 %lshr0, ptr addrspace(3) poison + store volatile i32 %lshr1, ptr addrspace(3) poison + store volatile i32 %lshr2, ptr addrspace(3) poison ret void } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll index d098b55b406af..7c54d303e91a3 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll @@ -1239,10 +1239,10 @@ define amdgpu_kernel void @test_call_external_p3_func_void() #0 { ; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_p3_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0 ; GCN-NEXT: [[COPY21:%[0-9]+]]:_(p3) = COPY $vgpr0 ; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc - ; GCN-NEXT: G_STORE [[COPY21]](p3), [[DEF]](p3) :: (volatile store (p3) into `ptr addrspace(3) undef`, addrspace 3) + ; GCN-NEXT: G_STORE [[COPY21]](p3), [[DEF]](p3) :: (volatile store (p3) into `ptr addrspace(3) poison`, addrspace 3) ; GCN-NEXT: S_ENDPGM 0 %val = call ptr addrspace(3) @external_p3_func_void() - store volatile ptr addrspace(3) %val, ptr addrspace(3) undef + store volatile ptr addrspace(3) %val, ptr addrspace(3) poison ret void } @@ -1299,10 +1299,10 @@ define amdgpu_kernel void @test_call_external_v2p3_func_void() #0 { ; GCN-NEXT: [[COPY22:%[0-9]+]]:_(p3) = COPY $vgpr1 ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[COPY21]](p3), [[COPY22]](p3) ; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc - ; GCN-NEXT: G_STORE [[BUILD_VECTOR]](<2 x p3>), [[DEF]](p3) :: (volatile store (<2 x p3>) into `ptr addrspace(3) undef`, addrspace 3) + ; GCN-NEXT: G_STORE [[BUILD_VECTOR]](<2 x p3>), [[DEF]](p3) :: (volatile store (<2 x p3>) into `ptr addrspace(3) poison`, addrspace 3) ; GCN-NEXT: S_ENDPGM 0 %val = call <2 x ptr addrspace(3)> @external_v2p3_func_void() - store volatile <2 x ptr addrspace(3)> %val, ptr addrspace(3) undef + store volatile <2 x ptr addrspace(3)> %val, ptr addrspace(3) poison ret void } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll index 2165fcfe08074..5d4f64f38bd2e 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll @@ -1699,13 +1699,13 @@ define void @void_func_byval_struct_i8_i32_x2(ptr addrspace(5) byval({ i8, i32 } ; CHECK-NEXT: G_STORE [[LOAD2]](s8), [[DEF]](p1) :: (volatile store (s8) into `ptr addrspace(1) poison`, align 4, addrspace 1) ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[DEF]], [[C1]](s64) ; CHECK-NEXT: G_STORE [[LOAD3]](s32), [[PTR_ADD3]](p1) :: (volatile store (s32) into `ptr addrspace(1) poison` + 4, addrspace 1) - ; CHECK-NEXT: G_STORE [[COPY2]](s32), [[DEF1]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3) + ; CHECK-NEXT: G_STORE [[COPY2]](s32), [[DEF1]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3) ; CHECK-NEXT: SI_RETURN %arg0.load = load volatile { i8, i32 }, ptr addrspace(5) %arg0 %arg1.load = load volatile { i8, i32 }, ptr addrspace(5) %arg1 store volatile { i8, i32 } %arg0.load, ptr addrspace(1) poison store volatile { i8, i32 } %arg1.load, ptr addrspace(1) poison - store volatile i32 %arg2, ptr addrspace(3) undef + store volatile i32 %arg2, ptr addrspace(3) poison ret void } @@ -2540,18 +2540,18 @@ define void @void_func_v3f32_wasted_reg(<3 x float> %arg0, i32 %arg1) #0 { ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[C]](s32) ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[C1]](s32) ; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[C2]](s32) - ; CHECK-NEXT: G_STORE [[EVEC]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3) - ; CHECK-NEXT: G_STORE [[EVEC1]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3) - ; CHECK-NEXT: G_STORE [[EVEC2]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3) - ; CHECK-NEXT: G_STORE [[COPY3]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3) + ; CHECK-NEXT: G_STORE [[EVEC]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3) + ; CHECK-NEXT: G_STORE [[EVEC1]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3) + ; CHECK-NEXT: G_STORE [[EVEC2]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3) + ; CHECK-NEXT: G_STORE [[COPY3]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3) ; CHECK-NEXT: SI_RETURN %arg0.0 = extractelement <3 x float> %arg0, i32 0 %arg0.1 = extractelement <3 x float> %arg0, i32 1 %arg0.2 = extractelement <3 x float> %arg0, i32 2 - store volatile float %arg0.0, ptr addrspace(3) undef - store volatile float %arg0.1, ptr addrspace(3) undef - store volatile float %arg0.2, ptr addrspace(3) undef - store volatile i32 %arg1, ptr addrspace(3) undef + store volatile float %arg0.0, ptr addrspace(3) poison + store volatile float %arg0.1, ptr addrspace(3) poison + store volatile float %arg0.2, ptr addrspace(3) poison + store volatile i32 %arg1, ptr addrspace(3) poison ret void } @@ -2572,18 +2572,18 @@ define void @void_func_v3i32_wasted_reg(<3 x i32> %arg0, i32 %arg1) #0 { ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[C]](s32) ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[C1]](s32) ; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[C2]](s32) - ; CHECK-NEXT: G_STORE [[EVEC]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3) - ; CHECK-NEXT: G_STORE [[EVEC1]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3) - ; CHECK-NEXT: G_STORE [[EVEC2]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3) - ; CHECK-NEXT: G_STORE [[COPY3]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3) + ; CHECK-NEXT: G_STORE [[EVEC]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3) + ; CHECK-NEXT: G_STORE [[EVEC1]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3) + ; CHECK-NEXT: G_STORE [[EVEC2]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3) + ; CHECK-NEXT: G_STORE [[COPY3]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3) ; CHECK-NEXT: SI_RETURN %arg0.0 = extractelement <3 x i32> %arg0, i32 0 %arg0.1 = extractelement <3 x i32> %arg0, i32 1 %arg0.2 = extractelement <3 x i32> %arg0, i32 2 - store volatile i32 %arg0.0, ptr addrspace(3) undef - store volatile i32 %arg0.1, ptr addrspace(3) undef - store volatile i32 %arg0.2, ptr addrspace(3) undef - store volatile i32 %arg1, ptr addrspace(3) undef + store volatile i32 %arg0.0, ptr addrspace(3) poison + store volatile i32 %arg0.1, ptr addrspace(3) poison + store volatile i32 %arg0.2, ptr addrspace(3) poison + store volatile i32 %arg1, ptr addrspace(3) poison ret void } diff --git a/llvm/test/CodeGen/AMDGPU/add.ll b/llvm/test/CodeGen/AMDGPU/add.ll index cd5b585a8c4e2..58a2ab08f2011 100644 --- a/llvm/test/CodeGen/AMDGPU/add.ll +++ b/llvm/test/CodeGen/AMDGPU/add.ll @@ -1389,7 +1389,7 @@ define amdgpu_ps void @add_select_vop3(i32 inreg %s, i32 %v) { ; GFX12-NEXT: s_endpgm %vcc = call i64 asm sideeffect "; def vcc", "={vcc}"() %sub = add i32 %v, %s - store i32 %sub, ptr addrspace(3) undef + store i32 %sub, ptr addrspace(3) poison call void asm sideeffect "; use vcc", "{vcc}"(i64 %vcc) ret void } diff --git a/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll b/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll index 3116b5d59a097..f4b2969475d82 100644 --- a/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll +++ b/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll @@ -863,7 +863,7 @@ bb16: ; preds = %bb58, %bb14 %i34 = getelementptr inbounds [16 x half], ptr addrspace(1) null, i64 %i24, i64 14 %i36 = load volatile <2 x half>, ptr addrspace(1) %i34, align 4 %i43 = load volatile <2 x float>, ptr addrspace(3) null, align 8 - %i46 = load volatile <2 x float>, ptr addrspace(3) undef, align 32 + %i46 = load volatile <2 x float>, ptr addrspace(3) poison, align 32 fence syncscope("workgroup") acquire br i1 %i11, label %bb58, label %bb51 diff --git a/llvm/test/CodeGen/AMDGPU/branch-condition-and.ll b/llvm/test/CodeGen/AMDGPU/branch-condition-and.ll index d23d7a7c8e0c8..2bf4a2c028fdc 100644 --- a/llvm/test/CodeGen/AMDGPU/branch-condition-and.ll +++ b/llvm/test/CodeGen/AMDGPU/branch-condition-and.ll @@ -31,7 +31,7 @@ bb: br i1 %tmp3, label %bb4, label %bb5 bb4: ; preds = %bb - store volatile i32 4, ptr addrspace(3) undef + store volatile i32 4, ptr addrspace(3) poison unreachable bb5: ; preds = %bb diff --git a/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll b/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll index 49f9f695409b1..cf82b569b4839 100644 --- a/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll +++ b/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll @@ -607,7 +607,7 @@ done: ; OPT-LABEL: @test_wrong_operand_local_small_offset_cmpxchg_i32( ; OPT: %in.gep = getelementptr i32, ptr addrspace(3) %in, i32 7 ; OPT: br i1 -; OPT: cmpxchg ptr addrspace(3) undef, ptr addrspace(3) %in.gep, ptr addrspace(3) undef seq_cst monotonic +; OPT: cmpxchg ptr addrspace(3) poison, ptr addrspace(3) %in.gep, ptr addrspace(3) poison seq_cst monotonic define amdgpu_kernel void @test_wrong_operand_local_small_offset_cmpxchg_i32(ptr addrspace(3) %out, ptr addrspace(3) %in) { entry: %out.gep = getelementptr ptr addrspace(3), ptr addrspace(3) %out, i32 999999 @@ -617,7 +617,7 @@ entry: br i1 %tmp0, label %endif, label %if if: - %tmp1.struct = cmpxchg ptr addrspace(3) undef, ptr addrspace(3) %in.gep, ptr addrspace(3) undef seq_cst monotonic + %tmp1.struct = cmpxchg ptr addrspace(3) poison, ptr addrspace(3) %in.gep, ptr addrspace(3) poison seq_cst monotonic %tmp1 = extractvalue { ptr addrspace(3), i1 } %tmp1.struct, 0 br label %endif diff --git a/llvm/test/CodeGen/AMDGPU/concat_vectors.ll b/llvm/test/CodeGen/AMDGPU/concat_vectors.ll index a9e4c8991bb2b..9e08a044e3687 100644 --- a/llvm/test/CodeGen/AMDGPU/concat_vectors.ll +++ b/llvm/test/CodeGen/AMDGPU/concat_vectors.ll @@ -313,7 +313,7 @@ define amdgpu_kernel void @concat_vector_crash2(ptr addrspace(1) %out, ptr addrs ; VI: ds_write_b128 define amdgpu_kernel void @build_vector_splat_concat_v8i16() { entry: - store <8 x i16> zeroinitializer, ptr addrspace(3) undef, align 16 + store <8 x i16> zeroinitializer, ptr addrspace(3) poison, align 16 store <8 x i16> zeroinitializer, ptr addrspace(3) null, align 16 ret void } diff --git a/llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll b/llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll index d6fb86dbd418e..b81392d4dea64 100644 --- a/llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll +++ b/llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll @@ -66,12 +66,12 @@ define amdgpu_kernel void @divergent_if_endif(ptr addrspace(1) %out) #0 { entry: %tid = call i32 @llvm.amdgcn.workitem.id.x() - %load0 = load volatile i32, ptr addrspace(3) undef + %load0 = load volatile i32, ptr addrspace(3) poison %cmp0 = icmp eq i32 %tid, 0 br i1 %cmp0, label %if, label %endif if: - %load1 = load volatile i32, ptr addrspace(3) undef + %load1 = load volatile i32, ptr addrspace(3) poison %val = add i32 %load0, %load1 br label %endif @@ -145,7 +145,7 @@ entry: loop: %i = phi i32 [ %i.inc, %loop ], [ 0, %entry ] %val = phi i32 [ %val.sub, %loop ], [ %load0, %entry ] - %load1 = load volatile i32, ptr addrspace(3) undef + %load1 = load volatile i32, ptr addrspace(3) poison %i.inc = add i32 %i, 1 %val.sub = sub i32 %val, %load1 %cmp1 = icmp ne i32 %i, 256 @@ -257,12 +257,12 @@ entry: br i1 %cmp0, label %if, label %else if: - %load1 = load volatile i32, ptr addrspace(3) undef + %load1 = load volatile i32, ptr addrspace(3) poison %val0 = add i32 %load0, %load1 br label %endif else: - %load2 = load volatile i32, ptr addrspace(3) undef + %load2 = load volatile i32, ptr addrspace(3) poison %val1 = sub i32 %load0, %load2 br label %endif diff --git a/llvm/test/CodeGen/AMDGPU/fminnum.f64.ll b/llvm/test/CodeGen/AMDGPU/fminnum.f64.ll index c563b4ab2dd29..92597594123ee 100644 --- a/llvm/test/CodeGen/AMDGPU/fminnum.f64.ll +++ b/llvm/test/CodeGen/AMDGPU/fminnum.f64.ll @@ -47,10 +47,10 @@ define amdgpu_kernel void @test_fmin_f64_ieee_flush([8 x i32], double %a, [8 x i ; GCN-NOT: [[RESULT]] ; GCN: ds_write_b64 v{{[0-9]+}}, [[RESULT]] define amdgpu_ps void @test_fmin_f64_no_ieee() nounwind { - %a = load volatile double, ptr addrspace(3) undef - %b = load volatile double, ptr addrspace(3) undef + %a = load volatile double, ptr addrspace(3) poison + %b = load volatile double, ptr addrspace(3) poison %val = call double @llvm.minnum.f64(double %a, double %b) #0 - store volatile double %val, ptr addrspace(3) undef + store volatile double %val, ptr addrspace(3) poison ret void } diff --git a/llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll b/llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll index 829d7432df2cc..0ee9a211e7826 100644 --- a/llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll +++ b/llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll @@ -180,7 +180,7 @@ define amdgpu_ps void @raw_buffer_atomic_min_rtn_f64(<4 x i32> inreg %rsrc, doub ; G_GFX1030-NEXT: s_endpgm main_body: %ret = call double @llvm.amdgcn.raw.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0) - store double %ret, ptr addrspace(3) undef + store double %ret, ptr addrspace(3) poison ret void } @@ -417,7 +417,7 @@ define amdgpu_ps void @raw_buffer_atomic_max_rtn_f64(<4 x i32> inreg %rsrc, doub ; G_GFX1030-NEXT: s_endpgm main_body: %ret = call double @llvm.amdgcn.raw.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0) - store double %ret, ptr addrspace(3) undef + store double %ret, ptr addrspace(3) poison ret void } diff --git a/llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll b/llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll index 0881cd84a4da2..f9e5e3ab1b216 100644 --- a/llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll +++ b/llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll @@ -180,7 +180,7 @@ define amdgpu_ps void @raw_ptr_buffer_atomic_min_rtn_f64(ptr addrspace(8) inreg ; G_GFX1030-NEXT: s_endpgm main_body: %ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fmin.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0) - store double %ret, ptr addrspace(3) undef + store double %ret, ptr addrspace(3) poison ret void } @@ -417,7 +417,7 @@ define amdgpu_ps void @raw_ptr_buffer_atomic_max_rtn_f64(ptr addrspace(8) inreg ; G_GFX1030-NEXT: s_endpgm main_body: %ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fmax.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0) - store double %ret, ptr addrspace(3) undef + store double %ret, ptr addrspace(3) poison ret void } diff --git a/llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll b/llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll index aa5f72a15c2f3..ea33925117aea 100644 --- a/llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll +++ b/llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll @@ -21,7 +21,7 @@ ; GCN: ds_write_b32 v0, v0 define void @func_mov_fi_i32() #0 { %alloca = alloca i32, addrspace(5) - store volatile ptr addrspace(5) %alloca, ptr addrspace(3) undef + store volatile ptr addrspace(5) %alloca, ptr addrspace(3) poison ret void } @@ -47,8 +47,8 @@ define void @func_mov_fi_i32() #0 { define void @func_mov_fi_i32_offset() #0 { %alloca0 = alloca i32, addrspace(5) %alloca1 = alloca i32, addrspace(5) - store volatile ptr addrspace(5) %alloca0, ptr addrspace(3) undef - store volatile ptr addrspace(5) %alloca1, ptr addrspace(3) undef + store volatile ptr addrspace(5) %alloca0, ptr addrspace(3) poison + store volatile ptr addrspace(5) %alloca1, ptr addrspace(3) poison ret void } @@ -72,7 +72,7 @@ define void @func_mov_fi_i32_offset() #0 { define void @func_add_constant_to_fi_i32() #0 { %alloca = alloca [2 x i32], align 4, addrspace(5) %gep0 = getelementptr inbounds [2 x i32], ptr addrspace(5) %alloca, i32 0, i32 1 - store volatile ptr addrspace(5) %gep0, ptr addrspace(3) undef + store volatile ptr addrspace(5) %gep0, ptr addrspace(3) poison ret void } @@ -95,7 +95,7 @@ define void @func_other_fi_user_i32() #0 { %alloca = alloca [2 x i32], align 4, addrspace(5) %ptrtoint = ptrtoint ptr addrspace(5) %alloca to i32 %mul = mul i32 %ptrtoint, 9 - store volatile i32 %mul, ptr addrspace(3) undef + store volatile i32 %mul, ptr addrspace(3) poison ret void } @@ -134,7 +134,7 @@ define void @void_func_byval_struct_i8_i32_ptr(ptr addrspace(5) byval({ i8, i32 %gep0 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %arg0, i32 0, i32 0 %gep1 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %arg0, i32 0, i32 1 %load1 = load i32, ptr addrspace(5) %gep1 - store volatile ptr addrspace(5) %gep1, ptr addrspace(3) undef + store volatile ptr addrspace(5) %gep1, ptr addrspace(3) poison ret void } @@ -149,8 +149,8 @@ define void @void_func_byval_struct_i8_i32_ptr_value(ptr addrspace(5) byval({ i8 %gep1 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %arg0, i32 0, i32 1 %load0 = load i8, ptr addrspace(5) %gep0 %load1 = load i32, ptr addrspace(5) %gep1 - store volatile i8 %load0, ptr addrspace(3) undef - store volatile i32 %load1, ptr addrspace(3) undef + store volatile i8 %load0, ptr addrspace(3) poison + store volatile i32 %load1, ptr addrspace(3) poison ret void } @@ -179,7 +179,7 @@ bb: %gep0 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %arg0, i32 0, i32 0 %gep1 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %arg0, i32 0, i32 1 %load1 = load volatile i32, ptr addrspace(5) %gep1 - store volatile ptr addrspace(5) %gep1, ptr addrspace(3) undef + store volatile ptr addrspace(5) %gep1, ptr addrspace(3) poison br label %ret ret: @@ -207,7 +207,7 @@ define void @func_other_fi_user_non_inline_imm_offset_i32() #0 { store volatile i32 7, ptr addrspace(5) %gep0 %ptrtoint = ptrtoint ptr addrspace(5) %alloca1 to i32 %mul = mul i32 %ptrtoint, 9 - store volatile i32 %mul, ptr addrspace(3) undef + store volatile i32 %mul, ptr addrspace(3) poison ret void } @@ -232,7 +232,7 @@ define void @func_other_fi_user_non_inline_imm_offset_i32_vcc_live() #0 { call void asm sideeffect "; use $0", "{vcc}"(i64 %vcc) %ptrtoint = ptrtoint ptr addrspace(5) %alloca1 to i32 %mul = mul i32 %ptrtoint, 9 - store volatile i32 %mul, ptr addrspace(3) undef + store volatile i32 %mul, ptr addrspace(3) poison ret void } @@ -292,7 +292,7 @@ bb: %gep0 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %alloca0, i32 0, i32 0 %gep1 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %alloca0, i32 0, i32 1 %load1 = load volatile i32, ptr addrspace(5) %gep1 - store volatile ptr addrspace(5) %gep1, ptr addrspace(3) undef + store volatile ptr addrspace(5) %gep1, ptr addrspace(3) poison br label %ret ret: diff --git a/llvm/test/CodeGen/AMDGPU/function-args.ll b/llvm/test/CodeGen/AMDGPU/function-args.ll index e2e263af4294f..8ee52a828de65 100644 --- a/llvm/test/CodeGen/AMDGPU/function-args.ll +++ b/llvm/test/CodeGen/AMDGPU/function-args.ll @@ -2562,7 +2562,7 @@ define void @void_func_byval_struct_i8_i32_x2(ptr addrspace(5) byval({ i8, i32 } %arg1.load = load volatile { i8, i32 }, ptr addrspace(5) %arg1 store volatile { i8, i32 } %arg0.load, ptr addrspace(1) poison store volatile { i8, i32 } %arg1.load, ptr addrspace(1) poison - store volatile i32 %arg2, ptr addrspace(3) undef + store volatile i32 %arg2, ptr addrspace(3) poison ret void } @@ -3780,10 +3780,10 @@ define void @void_func_v3f32_wasted_reg(<3 x float> %arg0, i32 %arg1) #0 { %arg0.0 = extractelement <3 x float> %arg0, i32 0 %arg0.1 = extractelement <3 x float> %arg0, i32 1 %arg0.2 = extractelement <3 x float> %arg0, i32 2 - store volatile float %arg0.0, ptr addrspace(3) undef - store volatile float %arg0.1, ptr addrspace(3) undef - store volatile float %arg0.2, ptr addrspace(3) undef - store volatile i32 %arg1, ptr addrspace(3) undef + store volatile float %arg0.0, ptr addrspace(3) poison + store volatile float %arg0.1, ptr addrspace(3) poison + store volatile float %arg0.2, ptr addrspace(3) poison + store volatile i32 %arg1, ptr addrspace(3) poison ret void } @@ -3832,10 +3832,10 @@ define void @void_func_v3i32_wasted_reg(<3 x i32> %arg0, i32 %arg1) #0 { %arg0.0 = extractelement <3 x i32> %arg0, i32 0 %arg0.1 = extractelement <3 x i32> %arg0, i32 1 %arg0.2 = extractelement <3 x i32> %arg0, i32 2 - store volatile i32 %arg0.0, ptr addrspace(3) undef - store volatile i32 %arg0.1, ptr addrspace(3) undef - store volatile i32 %arg0.2, ptr addrspace(3) undef - store volatile i32 %arg1, ptr addrspace(3) undef + store volatile i32 %arg0.0, ptr addrspace(3) poison + store volatile i32 %arg0.1, ptr addrspace(3) poison + store volatile i32 %arg0.2, ptr addrspace(3) poison + store volatile i32 %arg1, ptr addrspace(3) poison ret void } diff --git a/llvm/test/CodeGen/AMDGPU/function-returns.ll b/llvm/test/CodeGen/AMDGPU/function-returns.ll index 0400dce8fe032..8d459fc11473b 100644 --- a/llvm/test/CodeGen/AMDGPU/function-returns.ll +++ b/llvm/test/CodeGen/AMDGPU/function-returns.ll @@ -2202,10 +2202,10 @@ define { <3 x i32>, i32 } @v3i32_struct_func_void_wasted_reg() #0 { ; GFX11-NEXT: ds_load_b32 v3, v0 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] - %load0 = load volatile i32, ptr addrspace(3) undef - %load1 = load volatile i32, ptr addrspace(3) undef - %load2 = load volatile i32, ptr addrspace(3) undef - %load3 = load volatile i32, ptr addrspace(3) undef + %load0 = load volatile i32, ptr addrspace(3) poison + %load1 = load volatile i32, ptr addrspace(3) poison + %load2 = load volatile i32, ptr addrspace(3) poison + %load3 = load volatile i32, ptr addrspace(3) poison %insert.0 = insertelement <3 x i32> poison, i32 %load0, i32 0 %insert.1 = insertelement <3 x i32> %insert.0, i32 %load1, i32 1 @@ -2261,10 +2261,10 @@ define { <3 x float>, i32 } @v3f32_struct_func_void_wasted_reg() #0 { ; GFX11-NEXT: ds_load_b32 v3, v0 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] - %load0 = load volatile float, ptr addrspace(3) undef - %load1 = load volatile float, ptr addrspace(3) undef - %load2 = load volatile float, ptr addrspace(3) undef - %load3 = load volatile i32, ptr addrspace(3) undef + %load0 = load volatile float, ptr addrspace(3) poison + %load1 = load volatile float, ptr addrspace(3) poison + %load2 = load volatile float, ptr addrspace(3) poison + %load3 = load volatile i32, ptr addrspace(3) poison %insert.0 = insertelement <3 x float> poison, float %load0, i32 0 %insert.1 = insertelement <3 x float> %insert.0, float %load1, i32 1 @@ -2327,9 +2327,9 @@ define void @void_func_sret_max_known_zero_bits(ptr addrspace(5) sret(i8) %arg0) %lshr1 = lshr i32 %arg0.int, 17 %lshr2 = lshr i32 %arg0.int, 18 - store volatile i32 %lshr0, ptr addrspace(3) undef - store volatile i32 %lshr1, ptr addrspace(3) undef - store volatile i32 %lshr2, ptr addrspace(3) undef + store volatile i32 %lshr0, ptr addrspace(3) poison + store volatile i32 %lshr1, ptr addrspace(3) poison + store volatile i32 %lshr2, ptr addrspace(3) poison ret void } diff --git a/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll b/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll index caac30df4c0e0..cb99ceba2fca5 100644 --- a/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll +++ b/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll @@ -7894,8 +7894,8 @@ bb: %tmp6 = extractelement <9 x i32> %tmp5, i32 1 %tmp7 = bitcast <9 x float> %tmp4 to <9 x i32> %tmp8 = extractelement <9 x i32> %tmp7, i32 5 - store volatile i32 %tmp6, ptr addrspace(3) undef, align 4 - store volatile i32 %tmp8, ptr addrspace(3) undef, align 4 + store volatile i32 %tmp6, ptr addrspace(3) poison, align 4 + store volatile i32 %tmp8, ptr addrspace(3) poison, align 4 ret void } diff --git a/llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll b/llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll index 93eb928b3f44f..77a76387d1049 100644 --- a/llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll +++ b/llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll @@ -81,7 +81,7 @@ define amdgpu_kernel void @test_kernel(i32 %val) #0 { br i1 %cmp, label %store, label %end store: - store volatile i32 %vreg, ptr addrspace(3) undef + store volatile i32 %vreg, ptr addrspace(3) poison ret void end: diff --git a/llvm/test/CodeGen/AMDGPU/loop_break.ll b/llvm/test/CodeGen/AMDGPU/loop_break.ll index df543aba950bb..e90bde0f43f98 100644 --- a/llvm/test/CodeGen/AMDGPU/loop_break.ll +++ b/llvm/test/CodeGen/AMDGPU/loop_break.ll @@ -107,7 +107,7 @@ define amdgpu_kernel void @undef_phi_cond_break_loop(i32 %arg) #0 { ; OPT-NEXT: br i1 [[TMP1]], label %[[BB9:.*]], label %[[BB1]] ; OPT: [[BB9]]: ; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP0]]) -; OPT-NEXT: store volatile i32 7, ptr addrspace(3) undef, align 4 +; OPT-NEXT: store volatile i32 7, ptr addrspace(3) poison, align 4 ; OPT-NEXT: ret void ; ; GCN-LABEL: undef_phi_cond_break_loop: @@ -164,7 +164,7 @@ Flow: ; preds = %bb4, %bb1 br i1 %my.tmp3, label %bb9, label %bb1 bb9: ; preds = %Flow - store volatile i32 7, ptr addrspace(3) undef + store volatile i32 7, ptr addrspace(3) poison ret void } @@ -197,7 +197,7 @@ define amdgpu_kernel void @constexpr_phi_cond_break_loop(i32 %arg) #0 { ; OPT-NEXT: br i1 [[TMP1]], label %[[BB9:.*]], label %[[BB1]] ; OPT: [[BB9]]: ; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP0]]) -; OPT-NEXT: store volatile i32 7, ptr addrspace(3) undef, align 4 +; OPT-NEXT: store volatile i32 7, ptr addrspace(3) poison, align 4 ; OPT-NEXT: ret void ; ; GCN-LABEL: constexpr_phi_cond_break_loop: @@ -259,7 +259,7 @@ Flow: ; preds = %bb4, %bb1 br i1 %my.tmp3, label %bb9, label %bb1 bb9: ; preds = %Flow - store volatile i32 7, ptr addrspace(3) undef + store volatile i32 7, ptr addrspace(3) poison ret void } @@ -288,7 +288,7 @@ define amdgpu_kernel void @true_phi_cond_break_loop(i32 %arg) #0 { ; OPT-NEXT: br i1 [[TMP1]], label %[[BB9:.*]], label %[[BB1]] ; OPT: [[BB9]]: ; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP0]]) -; OPT-NEXT: store volatile i32 7, ptr addrspace(3) undef, align 4 +; OPT-NEXT: store volatile i32 7, ptr addrspace(3) poison, align 4 ; OPT-NEXT: ret void ; ; GCN-LABEL: true_phi_cond_break_loop: @@ -349,7 +349,7 @@ Flow: ; preds = %bb4, %bb1 br i1 %my.tmp3, label %bb9, label %bb1 bb9: ; preds = %Flow - store volatile i32 7, ptr addrspace(3) undef + store volatile i32 7, ptr addrspace(3) poison ret void } @@ -378,7 +378,7 @@ define amdgpu_kernel void @false_phi_cond_break_loop(i32 %arg) #0 { ; OPT-NEXT: br i1 [[TMP1]], label %[[BB9:.*]], label %[[BB1]] ; OPT: [[BB9]]: ; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP0]]) -; OPT-NEXT: store volatile i32 7, ptr addrspace(3) undef, align 4 +; OPT-NEXT: store volatile i32 7, ptr addrspace(3) poison, align 4 ; OPT-NEXT: ret void ; ; GCN-LABEL: false_phi_cond_break_loop: @@ -439,7 +439,7 @@ Flow: ; preds = %bb4, %bb1 br i1 %my.tmp3, label %bb9, label %bb1 bb9: ; preds = %Flow - store volatile i32 7, ptr addrspace(3) undef + store volatile i32 7, ptr addrspace(3) poison ret void } @@ -472,7 +472,7 @@ define amdgpu_kernel void @invert_true_phi_cond_break_loop(i32 %arg) #0 { ; OPT-NEXT: br i1 [[TMP1]], label %[[BB9:.*]], label %[[BB1]] ; OPT: [[BB9]]: ; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP0]]) -; OPT-NEXT: store volatile i32 7, ptr addrspace(3) undef, align 4 +; OPT-NEXT: store volatile i32 7, ptr addrspace(3) poison, align 4 ; OPT-NEXT: ret void ; ; GCN-LABEL: invert_true_phi_cond_break_loop: @@ -534,7 +534,7 @@ Flow: ; preds = %bb4, %bb1 br i1 %my.tmp3, label %bb1, label %bb9 bb9: ; preds = %Flow - store volatile i32 7, ptr addrspace(3) undef + store volatile i32 7, ptr addrspace(3) poison ret void } diff --git a/llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.ll b/llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.ll index e7855a1137a4a..530ff6780e24e 100644 --- a/llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.ll +++ b/llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.ll @@ -22,6 +22,6 @@ entry: store double %tmp16, ptr addrspace(3) %gep2, align 8 %tmp17 = load <2 x double>, ptr addrspace(3) getelementptr inbounds ([9 x double], ptr addrspace(3) @L, i32 2, i32 1), align 8 %tmp19 = extractelement <2 x double> %tmp17, i32 1 - store double %tmp19, ptr addrspace(3) undef, align 8 + store double %tmp19, ptr addrspace(3) poison, align 8 ret void } diff --git a/llvm/test/CodeGen/AMDGPU/merge-store-crash.ll b/llvm/test/CodeGen/AMDGPU/merge-store-crash.ll index 66a217cb7be45..bda2cebfcef66 100644 --- a/llvm/test/CodeGen/AMDGPU/merge-store-crash.ll +++ b/llvm/test/CodeGen/AMDGPU/merge-store-crash.ll @@ -13,8 +13,8 @@ ; CHECK: tbuffer_store_format_xyzw v[0:3], define amdgpu_vs void @main(i32 inreg %arg) { main_body: - %tmp = load float, ptr addrspace(3) undef, align 4 - %tmp1 = load float, ptr addrspace(3) undef, align 4 + %tmp = load float, ptr addrspace(3) poison, align 4 + %tmp1 = load float, ptr addrspace(3) poison, align 4 store float %tmp, ptr addrspace(3) null, align 4 %tmp2 = bitcast float %tmp to i32 %tmp3 = add nuw nsw i32 0, 1 diff --git a/llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll b/llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll index 387bfef550e3d..803cae4a7f9cd 100644 --- a/llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll +++ b/llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll @@ -45,7 +45,7 @@ bb23: ; preds = %bb23, %bb %tmp31 = add i32 %tmp30, %arg16 %tmp37 = icmp ult i32 %tmp31, %arg13 %tmp44 = load float, ptr addrspace(1) poison, align 4 - store float %tmp44, ptr addrspace(3) undef, align 4 + store float %tmp44, ptr addrspace(3) poison, align 4 %tmp47 = add i32 %tmp24, %arg2 br i1 %tmp37, label %bb23, label %.loopexit } diff --git a/llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll b/llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll index e2f10db659ec6..41d907e5f5491 100644 --- a/llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll +++ b/llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll @@ -51,7 +51,7 @@ ; IR: br i1 %15, label %exit1, label %Flow2 ; IR: exit1: -; IR: store volatile i32 17, ptr addrspace(3) undef +; IR: store volatile i32 17, ptr addrspace(3) poison ; IR: br label %Flow2 ; IR: UnifiedReturnBlock: @@ -135,7 +135,7 @@ exit0: ; preds = %LeafBlock, %LeafBlock1 ret void exit1: ; preds = %LeafBlock, %LeafBlock1 - store volatile i32 17, ptr addrspace(3) undef + store volatile i32 17, ptr addrspace(3) poison ret void } @@ -190,7 +190,7 @@ exit0: ; preds = %LeafBlock, %LeafBlock1 unreachable exit1: ; preds = %LeafBlock, %LeafBlock1 - store volatile i32 17, ptr addrspace(3) undef + store volatile i32 17, ptr addrspace(3) poison unreachable } @@ -233,7 +233,7 @@ exit1: ; preds = %LeafBlock, %LeafBlock1 ; IR: br i1 %15, label %exit1, label %Flow2 ; IR: exit1: -; IR: store volatile i32 17, ptr addrspace(3) undef +; IR: store volatile i32 17, ptr addrspace(3) poison ; IR: br label %Flow2 ; IR: UnifiedReturnBlock: @@ -271,7 +271,7 @@ exit0: ; preds = %LeafBlock, %LeafBlock1 ret void exit1: ; preds = %LeafBlock, %LeafBlock1 - store volatile i32 17, ptr addrspace(3) undef + store volatile i32 17, ptr addrspace(3) poison ret void } @@ -320,7 +320,7 @@ exit0: ; preds = %LeafBlock, %LeafBlock1 ret void exit1: ; preds = %LeafBlock, %LeafBlock1 - store volatile i32 17, ptr addrspace(3) undef + store volatile i32 17, ptr addrspace(3) poison ret void } @@ -351,7 +351,7 @@ exit0: ; preds = %LeafBlock, %LeafBlock1 ret float 1.0 exit1: ; preds = %LeafBlock, %LeafBlock1 - store i32 17, ptr addrspace(3) undef + store i32 17, ptr addrspace(3) poison ret float 2.0 } @@ -393,7 +393,7 @@ exit0: ; preds = %LeafBlock, %LeafBlock1 ret float 1.0 exit1: ; preds = %LeafBlock, %LeafBlock1 - store i32 17, ptr addrspace(3) undef + store i32 17, ptr addrspace(3) poison ret float 2.0 } @@ -412,7 +412,7 @@ exit1: ; preds = %LeafBlock, %LeafBlock1 ; IR: br i1 %10, label %exit0, label %UnifiedReturnBlock ; IR: exit0: -; IR-NEXT: store volatile i32 17, ptr addrspace(3) undef +; IR-NEXT: store volatile i32 17, ptr addrspace(3) poison ; IR-NEXT: br label %UnifiedReturnBlock ; IR: Flow1: @@ -460,7 +460,7 @@ LeafBlock1: ; preds = %entry br i1 %SwitchLeaf2, label %exit0, label %exit1 exit0: ; preds = %LeafBlock, %LeafBlock1 - store volatile i32 17, ptr addrspace(3) undef + store volatile i32 17, ptr addrspace(3) poison ret void exit1: ; preds = %LeafBlock, %LeafBlock1 @@ -474,7 +474,7 @@ exit1: ; preds = %LeafBlock, %LeafBlock1 ; IR-LABEL: @indirect_multi_divergent_region_exit_ret_unreachable( ; IR: exit0: ; preds = %Flow2 -; IR-NEXT: store volatile i32 17, ptr addrspace(3) undef +; IR-NEXT: store volatile i32 17, ptr addrspace(3) poison ; IR-NEXT: br label %UnifiedReturnBlock @@ -516,7 +516,7 @@ LeafBlock1: ; preds = %entry br i1 %SwitchLeaf2, label %exit0, label %indirect.exit1 exit0: ; preds = %LeafBlock, %LeafBlock1 - store volatile i32 17, ptr addrspace(3) undef + store volatile i32 17, ptr addrspace(3) poison ret void indirect.exit1: @@ -560,7 +560,7 @@ LeafBlock1: ; preds = %entry br i1 %SwitchLeaf2, label %exit0, label %exit1 exit0: ; preds = %LeafBlock, %LeafBlock1 - store volatile i32 17, ptr addrspace(3) undef + store volatile i32 17, ptr addrspace(3) poison ret void exit1: ; preds = %LeafBlock, %LeafBlock1 @@ -580,11 +580,11 @@ divergent.multi.exit.region: br i1 %divergent.cond0, label %divergent.ret0, label %divergent.ret1 divergent.ret0: - store volatile i32 11, ptr addrspace(3) undef + store volatile i32 11, ptr addrspace(3) poison ret void divergent.ret1: - store volatile i32 42, ptr addrspace(3) undef + store volatile i32 42, ptr addrspace(3) poison ret void uniform.ret: @@ -619,11 +619,11 @@ divergent.endif: br label %divergent.ret0 divergent.ret0: - store volatile i32 11, ptr addrspace(3) undef + store volatile i32 11, ptr addrspace(3) poison ret void divergent.ret1: - store volatile i32 42, ptr addrspace(3) undef + store volatile i32 42, ptr addrspace(3) poison ret void uniform.ret: @@ -669,11 +669,11 @@ uniform.endif: br label %uniform.ret0 uniform.ret0: - store volatile i32 11, ptr addrspace(3) undef + store volatile i32 11, ptr addrspace(3) poison ret void uniform.ret1: - store volatile i32 42, ptr addrspace(3) undef + store volatile i32 42, ptr addrspace(3) poison ret void divergent.ret: diff --git a/llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll b/llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll index c302c901ba519..e1c2bde99eed2 100644 --- a/llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll +++ b/llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll @@ -83,7 +83,7 @@ define amdgpu_kernel void @reduced_nested_loop_conditions(ptr addrspace(3) captu ; IR-NEXT: br i1 [[MY_TMP14]], label %[[BB16:.*]], label %[[BB20:.*]] ; IR: [[BB16]]: ; IR-NEXT: [[MY_TMP17:%.*]] = extractelement <2 x i32> [[MY_TMP15]], i64 1 -; IR-NEXT: [[MY_TMP18:%.*]] = getelementptr inbounds i32, ptr addrspace(3) undef, i32 [[MY_TMP17]] +; IR-NEXT: [[MY_TMP18:%.*]] = getelementptr inbounds i32, ptr addrspace(3) poison, i32 [[MY_TMP17]] ; IR-NEXT: [[MY_TMP19:%.*]] = load volatile i32, ptr addrspace(3) [[MY_TMP18]], align 4 ; IR-NEXT: br label %[[BB20]] ; IR: [[BB20]]: @@ -129,7 +129,7 @@ bb13: ; preds = %bb8, %bb3 bb16: ; preds = %bb13 %my.tmp17 = extractelement <2 x i32> %my.tmp15, i64 1 - %my.tmp18 = getelementptr inbounds i32, ptr addrspace(3) undef, i32 %my.tmp17 + %my.tmp18 = getelementptr inbounds i32, ptr addrspace(3) poison, i32 %my.tmp17 %my.tmp19 = load volatile i32, ptr addrspace(3) %my.tmp18 br label %bb20 diff --git a/llvm/test/CodeGen/AMDGPU/packed-fp32.ll b/llvm/test/CodeGen/AMDGPU/packed-fp32.ll index 866abc10b5777..2039558b9fc7d 100644 --- a/llvm/test/CodeGen/AMDGPU/packed-fp32.ll +++ b/llvm/test/CodeGen/AMDGPU/packed-fp32.ll @@ -540,7 +540,7 @@ define amdgpu_kernel void @shuffle_neg_add_f32(ptr addrspace(1) %out, ptr addrsp bb: %vec0 = load volatile <2 x float>, ptr addrspace(3) %lds, align 8 %lds.gep1 = getelementptr inbounds <2 x float>, ptr addrspace(3) %lds, i32 1 - %f32 = load volatile float, ptr addrspace(3) undef, align 8 + %f32 = load volatile float, ptr addrspace(3) poison, align 8 %vec1 = load volatile <2 x float>, ptr addrspace(3) %lds.gep1, align 8 %vec1.neg = fsub <2 x float> , %vec1 %vec1.neg.swap = shufflevector <2 x float> %vec1.neg, <2 x float> poison, <2 x i32> diff --git a/llvm/test/CodeGen/AMDGPU/packed-op-sel.ll b/llvm/test/CodeGen/AMDGPU/packed-op-sel.ll index 4cdf7f01a259b..e7343c150ea70 100644 --- a/llvm/test/CodeGen/AMDGPU/packed-op-sel.ll +++ b/llvm/test/CodeGen/AMDGPU/packed-op-sel.ll @@ -647,7 +647,7 @@ define amdgpu_kernel void @bitcast_fneg_f32(ptr addrspace(1) %out, ptr addrspace ; GCN-NEXT: s_endpgm bb: %vec0 = load volatile <2 x half>, ptr addrspace(3) %lds, align 4 - %f32 = load volatile float, ptr addrspace(3) undef, align 4 + %f32 = load volatile float, ptr addrspace(3) poison, align 4 %neg.f32 = fsub float -0.0, %f32 %bc = bitcast float %neg.f32 to <2 x half> %result = fadd <2 x half> %vec0, %bc @@ -675,7 +675,7 @@ define amdgpu_kernel void @shuffle_bitcast_fneg_f32(ptr addrspace(1) %out, ptr a bb: %vec0 = load volatile <2 x half>, ptr addrspace(3) %lds, align 4 - %f32 = load volatile float, ptr addrspace(3) undef, align 4 + %f32 = load volatile float, ptr addrspace(3) poison, align 4 %neg.f32 = fsub float -0.0, %f32 %bc = bitcast float %neg.f32 to <2 x half> %shuf = shufflevector <2 x half> %bc, <2 x half> poison, <2 x i32> diff --git a/llvm/test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll b/llvm/test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll index aeff6117d8fd1..0e9ea0c341cd3 100644 --- a/llvm/test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll +++ b/llvm/test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll @@ -5,7 +5,7 @@ declare i32 @llvm.read_register.i32(metadata) #0 define amdgpu_kernel void @test_invalid_read_flat_scratch_lo(ptr addrspace(1) %out) nounwind { - store volatile i32 0, ptr addrspace(3) undef + store volatile i32 0, ptr addrspace(3) poison %m0 = call i32 @llvm.read_register.i32(metadata !0) store i32 %m0, ptr addrspace(1) %out ret void diff --git a/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll b/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll index 3506a4730cda1..f2c639f382bcc 100644 --- a/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll +++ b/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll @@ -5,7 +5,7 @@ declare i32 @llvm.read_register.i32(metadata) #0 define amdgpu_kernel void @test_invalid_read_exec(ptr addrspace(1) %out) nounwind { - store volatile i32 0, ptr addrspace(3) undef + store volatile i32 0, ptr addrspace(3) poison %m0 = call i32 @llvm.read_register.i32(metadata !0) store i32 %m0, ptr addrspace(1) %out ret void diff --git a/llvm/test/CodeGen/AMDGPU/read_register.ll b/llvm/test/CodeGen/AMDGPU/read_register.ll index 227a08ecc4dbe..63ae193aa9e62 100644 --- a/llvm/test/CodeGen/AMDGPU/read_register.ll +++ b/llvm/test/CodeGen/AMDGPU/read_register.ll @@ -9,7 +9,7 @@ declare i64 @llvm.read_register.i64(metadata) #0 ; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], m0 ; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[COPY]] define amdgpu_kernel void @test_read_m0(ptr addrspace(1) %out) #0 { - store volatile i32 0, ptr addrspace(3) undef + store volatile i32 0, ptr addrspace(3) poison %m0 = call i32 @llvm.read_register.i32(metadata !0) store i32 %m0, ptr addrspace(1) %out ret void diff --git a/llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll b/llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll index 1f0e8c65a15e4..51072c36dadd2 100644 --- a/llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll +++ b/llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll @@ -32,7 +32,7 @@ bb6: ; preds = %bb6, %bb3 br i1 %tmp14, label %bb6, label %bb4 bb15: ; preds = %bb4 - store <2 x i32> %tmp5, ptr addrspace(3) undef, align 8 + store <2 x i32> %tmp5, ptr addrspace(3) poison, align 8 br label %bb16 bb16: ; preds = %bb15, %bb4 diff --git a/llvm/test/CodeGen/AMDGPU/rename-disconnected-bug.ll b/llvm/test/CodeGen/AMDGPU/rename-disconnected-bug.ll index a6867d4df9a2c..3c57c52a032b2 100644 --- a/llvm/test/CodeGen/AMDGPU/rename-disconnected-bug.ll +++ b/llvm/test/CodeGen/AMDGPU/rename-disconnected-bug.ll @@ -28,6 +28,6 @@ B30.1: B30.2: %v3 = phi <4 x float> [ %sub, %B30.1 ], [ %v2, %B20.2 ] %ve0 = extractelement <4 x float> %v3, i32 0 - store float %ve0, ptr addrspace(3) undef, align 4 + store float %ve0, ptr addrspace(3) poison, align 4 ret void } diff --git a/llvm/test/CodeGen/AMDGPU/ret_jump.ll b/llvm/test/CodeGen/AMDGPU/ret_jump.ll index 52033b67af7c6..46828a17444ab 100644 --- a/llvm/test/CodeGen/AMDGPU/ret_jump.ll +++ b/llvm/test/CodeGen/AMDGPU/ret_jump.ll @@ -98,7 +98,7 @@ else: ; preds = %main_body br i1 %divergent.cond, label %ret.bb, label %unreachable.bb unreachable.bb: ; preds = %else - store volatile i32 8, ptr addrspace(3) undef + store volatile i32 8, ptr addrspace(3) poison unreachable ret.bb: ; preds = %else, %main_body diff --git a/llvm/test/CodeGen/AMDGPU/returnaddress.ll b/llvm/test/CodeGen/AMDGPU/returnaddress.ll index d55a9bf17eb7e..09243a50de433 100644 --- a/llvm/test/CodeGen/AMDGPU/returnaddress.ll +++ b/llvm/test/CodeGen/AMDGPU/returnaddress.ll @@ -58,7 +58,7 @@ exit: define void @func5() nounwind { entry: %tmp = tail call ptr @llvm.returnaddress(i32 2) - store volatile i32 0, ptr addrspace(3) undef, align 4 + store volatile i32 0, ptr addrspace(3) poison, align 4 unreachable } diff --git a/llvm/test/CodeGen/AMDGPU/select-undef.ll b/llvm/test/CodeGen/AMDGPU/select-undef.ll index 48317a95c743e..4719f1e1617ed 100644 --- a/llvm/test/CodeGen/AMDGPU/select-undef.ll +++ b/llvm/test/CodeGen/AMDGPU/select-undef.ll @@ -54,12 +54,12 @@ entry: loop: %phi = phi <6 x float> [ poison, %entry ], [ %add, %loop ] - %load = load volatile <6 x float>, ptr addrspace(3) undef + %load = load volatile <6 x float>, ptr addrspace(3) poison %add = fadd <6 x float> %load, %phi br i1 %cond, label %loop, label %ret ret: - store volatile <6 x float> %add, ptr addrspace(3) undef + store volatile <6 x float> %add, ptr addrspace(3) poison ret void } @@ -73,12 +73,12 @@ entry: loop: %phi = phi <6 x i32> [ poison, %entry ], [ %add, %loop ] - %load = load volatile <6 x i32>, ptr addrspace(3) undef + %load = load volatile <6 x i32>, ptr addrspace(3) poison %add = add <6 x i32> %load, %phi br i1 %cond, label %loop, label %ret ret: - store volatile <6 x i32> %add, ptr addrspace(3) undef + store volatile <6 x i32> %add, ptr addrspace(3) poison ret void } @@ -93,12 +93,12 @@ entry: loop: %phi = phi <5 x float> [ poison, %entry ], [ %add, %loop ] - %load = load volatile <5 x float>, ptr addrspace(3) undef + %load = load volatile <5 x float>, ptr addrspace(3) poison %add = fadd <5 x float> %load, %phi br i1 %cond, label %loop, label %ret ret: - store volatile <5 x float> %add, ptr addrspace(3) undef + store volatile <5 x float> %add, ptr addrspace(3) poison ret void } @@ -112,12 +112,12 @@ entry: loop: %phi = phi <5 x i32> [ poison, %entry ], [ %add, %loop ] - %load = load volatile <5 x i32>, ptr addrspace(3) undef + %load = load volatile <5 x i32>, ptr addrspace(3) poison %add = add <5 x i32> %load, %phi br i1 %cond, label %loop, label %ret ret: - store volatile <5 x i32> %add, ptr addrspace(3) undef + store volatile <5 x i32> %add, ptr addrspace(3) poison ret void } @@ -269,7 +269,7 @@ entry: loop: %phi = phi bfloat [ poison, %entry ], [ %add, %loop ] - %load = load volatile bfloat, ptr addrspace(3) undef + %load = load volatile bfloat, ptr addrspace(3) poison %bc.0 = bitcast bfloat %load to i16 %bc.1 = bitcast bfloat %phi to i16 %add.i = add i16 %bc.0, %bc.1 @@ -277,7 +277,7 @@ loop: br i1 %cond, label %loop, label %ret ret: - store volatile bfloat %add, ptr addrspace(3) undef + store volatile bfloat %add, ptr addrspace(3) poison ret void } @@ -291,7 +291,7 @@ entry: loop: %phi = phi <2 x bfloat> [ poison, %entry ], [ %add, %loop ] - %load = load volatile <2 x bfloat>, ptr addrspace(3) undef + %load = load volatile <2 x bfloat>, ptr addrspace(3) poison %bc.0 = bitcast <2 x bfloat> %load to <2 x i16> %bc.1 = bitcast <2 x bfloat> %phi to <2 x i16> %add.i = add <2 x i16> %bc.0, %bc.1 @@ -299,7 +299,7 @@ loop: br i1 %cond, label %loop, label %ret ret: - store volatile <2 x bfloat> %add, ptr addrspace(3) undef + store volatile <2 x bfloat> %add, ptr addrspace(3) poison ret void } @@ -313,7 +313,7 @@ entry: loop: %phi = phi <3 x bfloat> [ poison, %entry ], [ %add, %loop ] - %load = load volatile <3 x bfloat>, ptr addrspace(3) undef + %load = load volatile <3 x bfloat>, ptr addrspace(3) poison %bc.0 = bitcast <3 x bfloat> %load to <3 x i16> %bc.1 = bitcast <3 x bfloat> %phi to <3 x i16> %add.i = add <3 x i16> %bc.0, %bc.1 @@ -321,7 +321,7 @@ loop: br i1 %cond, label %loop, label %ret ret: - store volatile <3 x bfloat> %add, ptr addrspace(3) undef + store volatile <3 x bfloat> %add, ptr addrspace(3) poison ret void } @@ -335,7 +335,7 @@ entry: loop: %phi = phi <4 x bfloat> [ poison, %entry ], [ %add, %loop ] - %load = load volatile <4 x bfloat>, ptr addrspace(3) undef + %load = load volatile <4 x bfloat>, ptr addrspace(3) poison %bc.0 = bitcast <4 x bfloat> %load to <4 x i16> %bc.1 = bitcast <4 x bfloat> %phi to <4 x i16> %add.i = add <4 x i16> %bc.0, %bc.1 @@ -343,7 +343,7 @@ loop: br i1 %cond, label %loop, label %ret ret: - store volatile <4 x bfloat> %add, ptr addrspace(3) undef + store volatile <4 x bfloat> %add, ptr addrspace(3) poison ret void } @@ -357,7 +357,7 @@ entry: loop: %phi = phi <6 x bfloat> [ poison, %entry ], [ %add, %loop ] - %load = load volatile <6 x bfloat>, ptr addrspace(3) undef + %load = load volatile <6 x bfloat>, ptr addrspace(3) poison %bc.0 = bitcast <6 x bfloat> %load to <6 x i16> %bc.1 = bitcast <6 x bfloat> %phi to <6 x i16> %add.i = add <6 x i16> %bc.0, %bc.1 @@ -365,7 +365,7 @@ loop: br i1 %cond, label %loop, label %ret ret: - store volatile <6 x bfloat> %add, ptr addrspace(3) undef + store volatile <6 x bfloat> %add, ptr addrspace(3) poison ret void } @@ -379,7 +379,7 @@ entry: loop: %phi = phi <8 x bfloat> [ poison, %entry ], [ %add, %loop ] - %load = load volatile <8 x bfloat>, ptr addrspace(3) undef + %load = load volatile <8 x bfloat>, ptr addrspace(3) poison %bc.0 = bitcast <8 x bfloat> %load to <8 x i16> %bc.1 = bitcast <8 x bfloat> %phi to <8 x i16> %add.i = add <8 x i16> %bc.0, %bc.1 @@ -387,7 +387,7 @@ loop: br i1 %cond, label %loop, label %ret ret: - store volatile <8 x bfloat> %add, ptr addrspace(3) undef + store volatile <8 x bfloat> %add, ptr addrspace(3) poison ret void } @@ -401,7 +401,7 @@ entry: loop: %phi = phi <16 x bfloat> [ poison, %entry ], [ %add, %loop ] - %load = load volatile <16 x bfloat>, ptr addrspace(3) undef + %load = load volatile <16 x bfloat>, ptr addrspace(3) poison %bc.0 = bitcast <16 x bfloat> %load to <16 x i16> %bc.1 = bitcast <16 x bfloat> %phi to <16 x i16> %add.i = add <16 x i16> %bc.0, %bc.1 @@ -409,7 +409,7 @@ loop: br i1 %cond, label %loop, label %ret ret: - store volatile <16 x bfloat> %add, ptr addrspace(3) undef + store volatile <16 x bfloat> %add, ptr addrspace(3) poison ret void } @@ -423,7 +423,7 @@ entry: loop: %phi = phi <32 x bfloat> [ poison, %entry ], [ %add, %loop ] - %load = load volatile <32 x bfloat>, ptr addrspace(3) undef + %load = load volatile <32 x bfloat>, ptr addrspace(3) poison %bc.0 = bitcast <32 x bfloat> %load to <32 x i16> %bc.1 = bitcast <32 x bfloat> %phi to <32 x i16> %add.i = add <32 x i16> %bc.0, %bc.1 @@ -431,7 +431,7 @@ loop: br i1 %cond, label %loop, label %ret ret: - store volatile <32 x bfloat> %add, ptr addrspace(3) undef + store volatile <32 x bfloat> %add, ptr addrspace(3) poison ret void } diff --git a/llvm/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll b/llvm/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll index 13745d4d5b171..71bbf864f33d6 100644 --- a/llvm/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll +++ b/llvm/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll @@ -19,7 +19,7 @@ bb: br i1 %tmp63, label %unreachable, label %ret unreachable: - store volatile i32 0, ptr addrspace(3) undef, align 4 + store volatile i32 0, ptr addrspace(3) poison, align 4 unreachable ret: @@ -47,7 +47,7 @@ ret: ret void unreachable: - store volatile i32 0, ptr addrspace(3) undef, align 4 + store volatile i32 0, ptr addrspace(3) poison, align 4 unreachable } @@ -66,7 +66,7 @@ bb: br i1 %tmp63, label %unreachable, label %ret unreachable: - store volatile i32 0, ptr addrspace(3) undef, align 4 + store volatile i32 0, ptr addrspace(3) poison, align 4 unreachable ret: diff --git a/llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll b/llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll index 4e6aa03d91876..96757d39fc8f5 100644 --- a/llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll +++ b/llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll @@ -3,7 +3,7 @@ %struct.lds = type { [64 x ptr], [16 x i8] } @stored_lds_struct = addrspace(3) global %struct.lds undef, align 16 -@stored_lds_ptr = addrspace(3) global ptr addrspace(3) undef, align 4 +@stored_lds_ptr = addrspace(3) global ptr addrspace(3) poison, align 4 @stored_constant_ptr = addrspace(3) global ptr addrspace(4) undef, align 8 @stored_global_ptr = addrspace(3) global ptr addrspace(1) poison, align 8 diff --git a/llvm/test/CodeGen/AMDGPU/smrd.ll b/llvm/test/CodeGen/AMDGPU/smrd.ll index ef91f0058a69b..1f0dd30d020f1 100644 --- a/llvm/test/CodeGen/AMDGPU/smrd.ll +++ b/llvm/test/CodeGen/AMDGPU/smrd.ll @@ -692,7 +692,7 @@ main_body: br i1 undef, label %if1, label %endif1 if1: ; preds = %main_body - store i32 0, ptr addrspace(3) undef, align 4 + store i32 0, ptr addrspace(3) poison, align 4 br label %endif1 endif1: ; preds = %if1, %main_body diff --git a/llvm/test/CodeGen/AMDGPU/spill-m0.ll b/llvm/test/CodeGen/AMDGPU/spill-m0.ll index 3e16e5c283c59..808e356580891 100644 --- a/llvm/test/CodeGen/AMDGPU/spill-m0.ll +++ b/llvm/test/CodeGen/AMDGPU/spill-m0.ll @@ -174,7 +174,7 @@ define amdgpu_kernel void @restore_m0_lds(i32 %arg) { br i1 %cmp, label %ret, label %bb bb: - store volatile i64 %sval, ptr addrspace(3) undef + store volatile i64 %sval, ptr addrspace(3) poison call void asm sideeffect "; use $0", "{m0}"(i32 %m0) #0 br label %ret diff --git a/llvm/test/CodeGen/AMDGPU/sub.ll b/llvm/test/CodeGen/AMDGPU/sub.ll index 001c35ef30cc6..a3562a452b6f1 100644 --- a/llvm/test/CodeGen/AMDGPU/sub.ll +++ b/llvm/test/CodeGen/AMDGPU/sub.ll @@ -1068,7 +1068,7 @@ define amdgpu_ps void @sub_select_vop3(i32 inreg %s, i32 %v) { ; GFX12-NEXT: s_endpgm %vcc = call i64 asm sideeffect "; def vcc", "={vcc}"() %sub = sub i32 %v, %s - store i32 %sub, ptr addrspace(3) undef + store i32 %sub, ptr addrspace(3) poison call void asm sideeffect "; use vcc", "{vcc}"(i64 %vcc) ret void } diff --git a/llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll b/llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll index 5496a95d2b737..9b65303ae1a0a 100644 --- a/llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll +++ b/llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll @@ -34,7 +34,7 @@ B30.1: B30.2: %v3 = phi <4 x float> [ %sub, %B30.1 ], [ %v0, %B2 ] %ve0 = extractelement <4 x float> %v3, i32 0 - store float %ve0, ptr addrspace(3) undef, align 4 + store float %ve0, ptr addrspace(3) poison, align 4 ret void } diff --git a/llvm/test/CodeGen/AMDGPU/uniform-cfg.ll b/llvm/test/CodeGen/AMDGPU/uniform-cfg.ll index 610e530a8ad13..9a330a2683097 100644 --- a/llvm/test/CodeGen/AMDGPU/uniform-cfg.ll +++ b/llvm/test/CodeGen/AMDGPU/uniform-cfg.ll @@ -1066,7 +1066,7 @@ define amdgpu_kernel void @move_to_valu_i64_eq(ptr addrspace(1) %out) { ; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; VI-NEXT: s_endpgm - %cond = load volatile i64, ptr addrspace(3) undef + %cond = load volatile i64, ptr addrspace(3) poison %cmp0 = icmp eq i64 %cond, 0 br i1 %cmp0, label %if, label %else @@ -1120,7 +1120,7 @@ define amdgpu_kernel void @move_to_valu_i64_ne(ptr addrspace(1) %out) { ; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; VI-NEXT: s_endpgm - %cond = load volatile i64, ptr addrspace(3) undef + %cond = load volatile i64, ptr addrspace(3) poison %cmp0 = icmp ne i64 %cond, 0 br i1 %cmp0, label %if, label %else diff --git a/llvm/test/CodeGen/AMDGPU/valu-i1.ll b/llvm/test/CodeGen/AMDGPU/valu-i1.ll index 9a64a6d99f46f..35cd2663f523f 100644 --- a/llvm/test/CodeGen/AMDGPU/valu-i1.ll +++ b/llvm/test/CodeGen/AMDGPU/valu-i1.ll @@ -143,7 +143,7 @@ then: ret void exit: - store volatile i32 7, ptr addrspace(3) undef + store volatile i32 7, ptr addrspace(3) poison ret void } diff --git a/llvm/test/CodeGen/AMDGPU/waitcnt-flat.ll b/llvm/test/CodeGen/AMDGPU/waitcnt-flat.ll index 203f1633fd8a5..89d2b29d708f0 100644 --- a/llvm/test/CodeGen/AMDGPU/waitcnt-flat.ll +++ b/llvm/test/CodeGen/AMDGPU/waitcnt-flat.ll @@ -23,6 +23,6 @@ define amdgpu_kernel void @test(ptr %out, i32 %in) { ; GFX9-NEXT: ds_write_b32 [[LD]] define amdgpu_kernel void @test_waitcnt_type_flat_global(ptr addrspace(1) %in) { %val = load volatile i32, ptr addrspace(1) %in - store volatile i32 %val, ptr addrspace(3) undef + store volatile i32 %val, ptr addrspace(3) poison ret void } diff --git a/llvm/test/CodeGen/AMDGPU/wave32.ll b/llvm/test/CodeGen/AMDGPU/wave32.ll index 846e347a4947e..150b2aa170978 100644 --- a/llvm/test/CodeGen/AMDGPU/wave32.ll +++ b/llvm/test/CodeGen/AMDGPU/wave32.ll @@ -1626,7 +1626,7 @@ Flow: ; preds = %bb4, %bb1 br i1 %tmp3, label %bb1, label %bb9 bb9: ; preds = %Flow - store volatile i32 7, ptr addrspace(3) undef + store volatile i32 7, ptr addrspace(3) poison ret void }