From 9510c6a61d4a7b82b7651f43f8509952a276bc81 Mon Sep 17 00:00:00 2001 From: Michael Maitland Date: Tue, 10 Dec 2024 08:13:59 -0800 Subject: [PATCH 1/3] [RISCV][VLOPT] Make sure all instructions in isSupportedInstr has test coverage --- llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll | 414 ++++++++++++++++++- 1 file changed, 394 insertions(+), 20 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll b/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll index daea264cdf7d6..75f91aaf16f2c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll @@ -146,6 +146,257 @@ define @vrsub_vx( %a, i32 %b, iXLen %vl) { ret %2 } +define @vand_vi( %a, iXLen %vl) { +; NOVLOPT-LABEL: vand_vi: +; NOVLOPT: # %bb.0: +; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; NOVLOPT-NEXT: vand.vi v10, v8, 5 +; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; NOVLOPT-NEXT: vadd.vv v8, v10, v8 +; NOVLOPT-NEXT: ret +; +; VLOPT-LABEL: vand_vi: +; VLOPT: # %bb.0: +; VLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; VLOPT-NEXT: vand.vi v10, v8, 5 +; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; VLOPT-NEXT: vadd.vv v8, v10, v8 +; VLOPT-NEXT: ret + %1 = call @llvm.riscv.vand.nxv4i32.i32( poison, %a, i32 5, iXLen -1) + %2 = call @llvm.riscv.vadd.nxv4i32.nxv4i32( poison, %1, %a, iXLen %vl) + ret %2 +} + +define @vand_vv( %a, %b, iXLen %vl) { +; NOVLOPT-LABEL: vand_vv: +; NOVLOPT: # %bb.0: +; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; NOVLOPT-NEXT: vand.vv v8, v8, v10 +; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; NOVLOPT-NEXT: vadd.vv v8, v8, v10 +; NOVLOPT-NEXT: ret +; +; VLOPT-LABEL: vand_vv: +; VLOPT: # %bb.0: +; VLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; VLOPT-NEXT: vand.vv v8, v8, v10 +; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; VLOPT-NEXT: vadd.vv v8, v8, v10 +; VLOPT-NEXT: ret + %1 = call @llvm.riscv.vand.nxv4i32.nxv4i32( poison, %a, %b, iXLen -1) + %2 = call @llvm.riscv.vadd.nxv4i32.nxv4i32( poison, %1, %b, iXLen %vl) + ret %2 +} + +define @vand_vx( %a, i32 %b, iXLen %vl) { +; NOVLOPT-LABEL: vand_vx: +; NOVLOPT: # %bb.0: +; NOVLOPT-NEXT: vsetvli a2, zero, e32, m2, ta, ma +; NOVLOPT-NEXT: vand.vx v10, v8, a0 +; NOVLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma +; NOVLOPT-NEXT: vadd.vv v8, v10, v8 +; NOVLOPT-NEXT: ret +; +; VLOPT-LABEL: vand_vx: +; VLOPT: # %bb.0: +; VLOPT-NEXT: vsetvli a2, zero, e32, m2, ta, ma +; VLOPT-NEXT: vand.vx v10, v8, a0 +; VLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma +; VLOPT-NEXT: vadd.vv v8, v10, v8 +; VLOPT-NEXT: ret + %1 = call @llvm.riscv.vand.nxv4i32.i32( poison, %a, i32 %b, iXLen -1) + %2 = call @llvm.riscv.vadd.nxv4i32.nxv4i32( poison, %1, %a, iXLen %vl) + ret %2 +} + +define @vor_vi( %a, iXLen %vl) { +; NOVLOPT-LABEL: vor_vi: +; NOVLOPT: # %bb.0: +; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; NOVLOPT-NEXT: vor.vi v10, v8, 5 +; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; NOVLOPT-NEXT: vadd.vv v8, v10, v8 +; NOVLOPT-NEXT: ret +; +; VLOPT-LABEL: vor_vi: +; VLOPT: # %bb.0: +; VLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; VLOPT-NEXT: vor.vi v10, v8, 5 +; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; VLOPT-NEXT: vadd.vv v8, v10, v8 +; VLOPT-NEXT: ret + %1 = call @llvm.riscv.vor.nxv4i32.i32( poison, %a, i32 5, iXLen -1) + %2 = call @llvm.riscv.vadd.nxv4i32.nxv4i32( poison, %1, %a, iXLen %vl) + ret %2 +} + +define @vor_vv( %a, %b, iXLen %vl) { +; NOVLOPT-LABEL: vor_vv: +; NOVLOPT: # %bb.0: +; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; NOVLOPT-NEXT: vor.vv v8, v8, v10 +; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; NOVLOPT-NEXT: vadd.vv v8, v8, v10 +; NOVLOPT-NEXT: ret +; +; VLOPT-LABEL: vor_vv: +; VLOPT: # %bb.0: +; VLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; VLOPT-NEXT: vor.vv v8, v8, v10 +; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; VLOPT-NEXT: vadd.vv v8, v8, v10 +; VLOPT-NEXT: ret + %1 = call @llvm.riscv.vor.nxv4i32.nxv4i32( poison, %a, %b, iXLen -1) + %2 = call @llvm.riscv.vadd.nxv4i32.nxv4i32( poison, %1, %b, iXLen %vl) + ret %2 +} + +define @vor_vx( %a, i32 %b, iXLen %vl) { +; NOVLOPT-LABEL: vor_vx: +; NOVLOPT: # %bb.0: +; NOVLOPT-NEXT: vsetvli a2, zero, e32, m2, ta, ma +; NOVLOPT-NEXT: vor.vx v10, v8, a0 +; NOVLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma +; NOVLOPT-NEXT: vadd.vv v8, v10, v8 +; NOVLOPT-NEXT: ret +; +; VLOPT-LABEL: vor_vx: +; VLOPT: # %bb.0: +; VLOPT-NEXT: vsetvli a2, zero, e32, m2, ta, ma +; VLOPT-NEXT: vor.vx v10, v8, a0 +; VLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma +; VLOPT-NEXT: vadd.vv v8, v10, v8 +; VLOPT-NEXT: ret + %1 = call @llvm.riscv.vor.nxv4i32.i32( poison, %a, i32 %b, iXLen -1) + %2 = call @llvm.riscv.vadd.nxv4i32.nxv4i32( poison, %1, %a, iXLen %vl) + ret %2 +} + +define @vxor_vi( %a, iXLen %vl) { +; NOVLOPT-LABEL: vxor_vi: +; NOVLOPT: # %bb.0: +; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; NOVLOPT-NEXT: vxor.vi v10, v8, 5 +; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; NOVLOPT-NEXT: vadd.vv v8, v10, v8 +; NOVLOPT-NEXT: ret +; +; VLOPT-LABEL: vxor_vi: +; VLOPT: # %bb.0: +; VLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; VLOPT-NEXT: vxor.vi v10, v8, 5 +; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; VLOPT-NEXT: vadd.vv v8, v10, v8 +; VLOPT-NEXT: ret + %1 = call @llvm.riscv.vxor.nxv4i32.i32( poison, %a, i32 5, iXLen -1) + %2 = call @llvm.riscv.vadd.nxv4i32.nxv4i32( poison, %1, %a, iXLen %vl) + ret %2 +} + +define @vxor_vv( %a, %b, iXLen %vl) { +; NOVLOPT-LABEL: vxor_vv: +; NOVLOPT: # %bb.0: +; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; NOVLOPT-NEXT: vxor.vv v8, v8, v10 +; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; NOVLOPT-NEXT: vadd.vv v8, v8, v10 +; NOVLOPT-NEXT: ret +; +; VLOPT-LABEL: vxor_vv: +; VLOPT: # %bb.0: +; VLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; VLOPT-NEXT: vxor.vv v8, v8, v10 +; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; VLOPT-NEXT: vadd.vv v8, v8, v10 +; VLOPT-NEXT: ret + %1 = call @llvm.riscv.vxor.nxv4i32.nxv4i32( poison, %a, %b, iXLen -1) + %2 = call @llvm.riscv.vadd.nxv4i32.nxv4i32( poison, %1, %b, iXLen %vl) + ret %2 +} + +define @vxor_vx( %a, i32 %b, iXLen %vl) { +; NOVLOPT-LABEL: vxor_vx: +; NOVLOPT: # %bb.0: +; NOVLOPT-NEXT: vsetvli a2, zero, e32, m2, ta, ma +; NOVLOPT-NEXT: vxor.vx v10, v8, a0 +; NOVLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma +; NOVLOPT-NEXT: vadd.vv v8, v10, v8 +; NOVLOPT-NEXT: ret +; +; VLOPT-LABEL: vxor_vx: +; VLOPT: # %bb.0: +; VLOPT-NEXT: vsetvli a2, zero, e32, m2, ta, ma +; VLOPT-NEXT: vxor.vx v10, v8, a0 +; VLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma +; VLOPT-NEXT: vadd.vv v8, v10, v8 +; VLOPT-NEXT: ret + %1 = call @llvm.riscv.vxor.nxv4i32.nxv4i32( poison, %a, i32 %b, iXLen -1) + %2 = call @llvm.riscv.vadd.nxv4i32.nxv4i32( poison, %1, %a, iXLen %vl) + ret %2 +} + +define @vsll_vi( %a, iXLen %vl) { +; NOVLOPT-LABEL: vsll_vi: +; NOVLOPT: # %bb.0: +; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; NOVLOPT-NEXT: vsll.vi v10, v8, 5 +; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; NOVLOPT-NEXT: vadd.vv v8, v10, v8 +; NOVLOPT-NEXT: ret +; +; VLOPT-LABEL: vsll_vi: +; VLOPT: # %bb.0: +; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; VLOPT-NEXT: vsll.vi v10, v8, 5 +; VLOPT-NEXT: vadd.vv v8, v10, v8 +; VLOPT-NEXT: ret + %1 = call @llvm.riscv.vsll.nxv4i32( poison, %a, iXLen 5, iXLen -1) + %2 = call @llvm.riscv.vadd.nxv4i32.nxv4i32( poison, %1, %a, iXLen %vl) + ret %2 +} + +define @vsll_vv( %a, %b, iXLen %vl) { +; NOVLOPT-LABEL: vsll_vv: +; NOVLOPT: # %bb.0: +; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; NOVLOPT-NEXT: vsll.vv v8, v8, v10 +; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; NOVLOPT-NEXT: vadd.vv v8, v8, v10 +; NOVLOPT-NEXT: ret +; +; VLOPT-LABEL: vsll_vv: +; VLOPT: # %bb.0: +; VLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; VLOPT-NEXT: vsll.vv v8, v8, v10 +; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; VLOPT-NEXT: vadd.vv v8, v8, v10 +; VLOPT-NEXT: ret + %1 = call @llvm.riscv.vsll.nxv4i32.nxv4i32( poison, %a, %b, iXLen -1) + %2 = call @llvm.riscv.vadd.nxv4i32.nxv4i32( poison, %1, %b, iXLen %vl) + ret %2 +} + +define @vsll_vx( %a, iXLen %b, iXLen %vl) { +; NOVLOPT-LABEL: vsll_vx: +; NOVLOPT: # %bb.0: +; NOVLOPT-NEXT: vsetvli a2, zero, e32, m2, ta, ma +; NOVLOPT-NEXT: vsll.vx v10, v8, a0 +; NOVLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma +; NOVLOPT-NEXT: vadd.vv v8, v10, v8 +; NOVLOPT-NEXT: ret +; +; VLOPT-LABEL: vsll_vx: +; VLOPT: # %bb.0: +; VLOPT-NEXT: vsetvli a2, zero, e32, m2, ta, ma +; VLOPT-NEXT: vsll.vx v10, v8, a0 +; VLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma +; VLOPT-NEXT: vadd.vv v8, v10, v8 +; VLOPT-NEXT: ret + %1 = call @llvm.riscv.vsll.nxv4i32.nxv4i32( poison, %a, iXLen %b, iXLen -1) + %2 = call @llvm.riscv.vadd.nxv4i32.nxv4i32( poison, %1, %a, iXLen %vl) + ret %2 +} + define @vwaddu_vv( %a, %b, iXLen %vl) { ; NOVLOPT-LABEL: vwaddu_vv: ; NOVLOPT: # %bb.0: @@ -167,6 +418,132 @@ define @vwaddu_vv( %a, % ret %2 } +define @vsrl_vi( %a, iXLen %vl) { +; NOVLOPT-LABEL: vsrl_vi: +; NOVLOPT: # %bb.0: +; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; NOVLOPT-NEXT: vsrl.vi v10, v8, 5 +; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; NOVLOPT-NEXT: vadd.vv v8, v10, v8 +; NOVLOPT-NEXT: ret +; +; VLOPT-LABEL: vsrl_vi: +; VLOPT: # %bb.0: +; VLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; VLOPT-NEXT: vsrl.vi v10, v8, 5 +; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; VLOPT-NEXT: vadd.vv v8, v10, v8 +; VLOPT-NEXT: ret + %1 = call @llvm.riscv.vsrl.nxv4i32.nxv4i32( poison, %a, iXLen 5, iXLen -1) + %2 = call @llvm.riscv.vadd.nxv4i32.nxv4i32( poison, %1, %a, iXLen %vl) + ret %2 +} + +define @vsrl_vv( %a, %b, iXLen %vl) { +; NOVLOPT-LABEL: vsrl_vv: +; NOVLOPT: # %bb.0: +; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; NOVLOPT-NEXT: vsrl.vv v8, v8, v10 +; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; NOVLOPT-NEXT: vadd.vv v8, v8, v10 +; NOVLOPT-NEXT: ret +; +; VLOPT-LABEL: vsrl_vv: +; VLOPT: # %bb.0: +; VLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; VLOPT-NEXT: vsrl.vv v8, v8, v10 +; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; VLOPT-NEXT: vadd.vv v8, v8, v10 +; VLOPT-NEXT: ret + %1 = call @llvm.riscv.vsrl.nxv4i32.nxv4i32( poison, %a, %b, iXLen -1) + %2 = call @llvm.riscv.vadd.nxv4i32.nxv4i32( poison, %1, %b, iXLen %vl) + ret %2 +} + +define @vsrl_vx( %a, iXLen %b, iXLen %vl) { +; NOVLOPT-LABEL: vsrl_vx: +; NOVLOPT: # %bb.0: +; NOVLOPT-NEXT: vsetvli a2, zero, e32, m2, ta, ma +; NOVLOPT-NEXT: vsrl.vx v10, v8, a0 +; NOVLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma +; NOVLOPT-NEXT: vadd.vv v8, v10, v8 +; NOVLOPT-NEXT: ret +; +; VLOPT-LABEL: vsrl_vx: +; VLOPT: # %bb.0: +; VLOPT-NEXT: vsetvli a2, zero, e32, m2, ta, ma +; VLOPT-NEXT: vsrl.vx v10, v8, a0 +; VLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma +; VLOPT-NEXT: vadd.vv v8, v10, v8 +; VLOPT-NEXT: ret + %1 = call @llvm.riscv.vsrl.nxv4i32.nxv4i32( poison, %a, iXLen %b, iXLen -1) + %2 = call @llvm.riscv.vadd.nxv4i32.nxv4i32( poison, %1, %a, iXLen %vl) + ret %2 +} + +define @vsra_vi( %a, iXLen %vl) { +; NOVLOPT-LABEL: vsra_vi: +; NOVLOPT: # %bb.0: +; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; NOVLOPT-NEXT: vsra.vi v10, v8, 5 +; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; NOVLOPT-NEXT: vadd.vv v8, v10, v8 +; NOVLOPT-NEXT: ret +; +; VLOPT-LABEL: vsra_vi: +; VLOPT: # %bb.0: +; VLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; VLOPT-NEXT: vsra.vi v10, v8, 5 +; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; VLOPT-NEXT: vadd.vv v8, v10, v8 +; VLOPT-NEXT: ret + %1 = call @llvm.riscv.vsra.nxv4i32.nxv4i32( poison, %a, iXLen 5, iXLen -1) + %2 = call @llvm.riscv.vadd.nxv4i32.nxv4i32( poison, %1, %a, iXLen %vl) + ret %2 +} + +define @vsra_vv( %a, %b, iXLen %vl) { +; NOVLOPT-LABEL: vsra_vv: +; NOVLOPT: # %bb.0: +; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; NOVLOPT-NEXT: vsra.vv v8, v8, v10 +; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; NOVLOPT-NEXT: vadd.vv v8, v8, v10 +; NOVLOPT-NEXT: ret +; +; VLOPT-LABEL: vsra_vv: +; VLOPT: # %bb.0: +; VLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; VLOPT-NEXT: vsra.vv v8, v8, v10 +; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; VLOPT-NEXT: vadd.vv v8, v8, v10 +; VLOPT-NEXT: ret + %1 = call @llvm.riscv.vsra.nxv4i32.nxv4i32( poison, %a, %b, iXLen -1) + %2 = call @llvm.riscv.vadd.nxv4i32.nxv4i32( poison, %1, %b, iXLen %vl) + ret %2 +} + +define @vsra_vx( %a, iXLen %b, iXLen %vl) { +; NOVLOPT-LABEL: vsra_vx: +; NOVLOPT: # %bb.0: +; NOVLOPT-NEXT: vsetvli a2, zero, e32, m2, ta, ma +; NOVLOPT-NEXT: vsra.vx v10, v8, a0 +; NOVLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma +; NOVLOPT-NEXT: vadd.vv v8, v10, v8 +; NOVLOPT-NEXT: ret +; +; VLOPT-LABEL: vsra_vx: +; VLOPT: # %bb.0: +; VLOPT-NEXT: vsetvli a2, zero, e32, m2, ta, ma +; VLOPT-NEXT: vsra.vx v10, v8, a0 +; VLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma +; VLOPT-NEXT: vadd.vv v8, v10, v8 +; VLOPT-NEXT: ret + %1 = call @llvm.riscv.vsra.nxv4i32.nxv4i32( poison, %a, iXLen %b, iXLen -1) + %2 = call @llvm.riscv.vadd.nxv4i32.nxv4i32( poison, %1, %a, iXLen %vl) + ret %2 +} + define @vwaddu_vx( %a, i32 %b, iXLen %vl) { ; NOVLOPT-LABEL: vwaddu_vx: ; NOVLOPT: # %bb.0: @@ -602,26 +979,6 @@ define @vzext_vf8( %a, %b ret %2 } -define @vsll_vi( %a, iXLen %vl) { -; NOVLOPT-LABEL: vsll_vi: -; NOVLOPT: # %bb.0: -; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; NOVLOPT-NEXT: vsll.vi v10, v8, 5 -; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; NOVLOPT-NEXT: vadd.vv v8, v10, v8 -; NOVLOPT-NEXT: ret -; -; VLOPT-LABEL: vsll_vi: -; VLOPT: # %bb.0: -; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; VLOPT-NEXT: vsll.vi v10, v8, 5 -; VLOPT-NEXT: vadd.vv v8, v10, v8 -; VLOPT-NEXT: ret - %1 = call @llvm.riscv.vsll.nxv4i32.nxv4i32( poison, %a, iXLen 5, iXLen -1) - %2 = call @llvm.riscv.vadd.nxv4i32.nxv4i32( poison, %1, %a, iXLen %vl) - ret %2 -} - define @vnsrl_wi( %a, %b, iXLen %vl) { ; NOVLOPT-LABEL: vnsrl_wi: ; NOVLOPT: # %bb.0: @@ -1591,6 +1948,23 @@ define @vmv_v_i( %a, i32 %x, iXLen %vl) { ret %2 } +define @vmv_v_v( %a, %v, iXLen %vl) { +; NOVLOPT-LABEL: vmv_v_v: +; NOVLOPT: # %bb.0: +; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; NOVLOPT-NEXT: vadd.vv v8, v10, v8 +; NOVLOPT-NEXT: ret +; +; VLOPT-LABEL: vmv_v_v: +; VLOPT: # %bb.0: +; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; VLOPT-NEXT: vadd.vv v8, v10, v8 +; VLOPT-NEXT: ret + %1 = call @llvm.riscv.vmv.v.v.nxv4i32( poison, %v, iXLen -1) + %2 = call @llvm.riscv.vadd.nxv4i32.nxv4i32( poison, %1, %a, iXLen %vl) + ret %2 +} + define @vmv_v_x( %a, i32 %x, iXLen %vl) { ; NOVLOPT-LABEL: vmv_v_x: ; NOVLOPT: # %bb.0: From 1c9021893ae94d9430fe948802444dfd1f453872 Mon Sep 17 00:00:00 2001 From: Michael Maitland Date: Tue, 10 Dec 2024 09:59:48 -0800 Subject: [PATCH 2/3] fixup! fix vmv.v.v test --- llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll | 25 ++++++++++++-------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll b/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll index 75f91aaf16f2c..47ab07a153c6e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll @@ -1948,21 +1948,26 @@ define @vmv_v_i( %a, i32 %x, iXLen %vl) { ret %2 } -define @vmv_v_v( %a, %v, iXLen %vl) { -; NOVLOPT-LABEL: vmv_v_v: +; The vmv.v.v is optimized away if we use a vadd as the user. +define @vmv_v_v( %a, i8 %b, %c, %m, iXLen %vl) { +; NOVLOPT-LABEL: vmerge_vvm: ; NOVLOPT: # %bb.0: -; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; NOVLOPT-NEXT: vadd.vv v8, v10, v8 +; NOVLOPT-NEXT: vsetvli a2, zero, e8, mf8, tu, ma +; NOVLOPT-NEXT: vmv.v.x v8, a0 +; NOVLOPT-NEXT: vsetvli zero, a1, e8, mf8, ta, ma +; NOVLOPT-NEXT: vmerge.vvm v8, v8, v9, v0 ; NOVLOPT-NEXT: ret ; -; VLOPT-LABEL: vmv_v_v: +; VLOPT-LABEL: vmerge_vvm: ; VLOPT: # %bb.0: -; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; VLOPT-NEXT: vadd.vv v8, v10, v8 +; VLOPT-NEXT: vsetvli zero, a1, e8, mf8, tu, ma +; VLOPT-NEXT: vmv.v.x v8, a0 +; VLOPT-NEXT: vsetvli zero, zero, e8, mf8, ta, ma +; VLOPT-NEXT: vmerge.vvm v8, v8, v9, v0 ; VLOPT-NEXT: ret - %1 = call @llvm.riscv.vmv.v.v.nxv4i32( poison, %v, iXLen -1) - %2 = call @llvm.riscv.vadd.nxv4i32.nxv4i32( poison, %1, %a, iXLen %vl) - ret %2 + %2 = call @llvm.riscv.vmv.v.x.nxv1i8( %a, i8 %b, iXLen -1) + %3 = call @llvm.riscv.vmerge.nxv1i8.nxv1i8( undef, %2, %c, %m, iXLen %vl) + ret %3 } define @vmv_v_x( %a, i32 %x, iXLen %vl) { From 0e243274f52aa0b4dc951dbd0b01dfe5a16478ea Mon Sep 17 00:00:00 2001 From: Michael Maitland Date: Tue, 10 Dec 2024 13:11:04 -0800 Subject: [PATCH 3/3] fixup! respond to review --- llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 26 ++++-- llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll | 95 ++++++++------------ 2 files changed, 60 insertions(+), 61 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp index 62c21fce61c37..dabf36480f1dc 100644 --- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp +++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp @@ -499,6 +499,26 @@ static bool isSupportedInstr(const MachineInstr &MI) { case RISCV::VSUB_VX: case RISCV::VRSUB_VI: case RISCV::VRSUB_VX: + // Vector Bitwise Logical Instructions + // Vector Single-Width Shift Instructions + case RISCV::VAND_VI: + case RISCV::VAND_VV: + case RISCV::VAND_VX: + case RISCV::VOR_VI: + case RISCV::VOR_VV: + case RISCV::VOR_VX: + case RISCV::VXOR_VI: + case RISCV::VXOR_VV: + case RISCV::VXOR_VX: + case RISCV::VSLL_VI: + case RISCV::VSLL_VV: + case RISCV::VSLL_VX: + case RISCV::VSRL_VI: + case RISCV::VSRL_VV: + case RISCV::VSRL_VX: + case RISCV::VSRA_VI: + case RISCV::VSRA_VV: + case RISCV::VSRA_VX: // Vector Widening Integer Add/Subtract case RISCV::VWADDU_VV: case RISCV::VWADDU_VX: @@ -525,11 +545,6 @@ static bool isSupportedInstr(const MachineInstr &MI) { case RISCV::VSEXT_VF8: // Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions // FIXME: Add support - // Vector Bitwise Logical Instructions - // FIXME: Add support - // Vector Single-Width Shift Instructions - // FIXME: Add support - case RISCV::VSLL_VI: // Vector Narrowing Integer Right Shift Instructions // FIXME: Add support case RISCV::VNSRL_WI: @@ -592,6 +607,7 @@ static bool isSupportedInstr(const MachineInstr &MI) { // FIXME: Add support case RISCV::VMV_V_I: case RISCV::VMV_V_X: + case RISCV::VMV_V_V: // Vector Crypto case RISCV::VWSLL_VI: diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll b/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll index 47ab07a153c6e..0215e6a80d09a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll @@ -157,9 +157,8 @@ define @vand_vi( %a, iXLen %vl) { ; ; VLOPT-LABEL: vand_vi: ; VLOPT: # %bb.0: -; VLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; VLOPT-NEXT: vand.vi v10, v8, 5 ; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; VLOPT-NEXT: vand.vi v10, v8, 5 ; VLOPT-NEXT: vadd.vv v8, v10, v8 ; VLOPT-NEXT: ret %1 = call @llvm.riscv.vand.nxv4i32.i32( poison, %a, i32 5, iXLen -1) @@ -178,9 +177,8 @@ define @vand_vv( %a, %b, ; ; VLOPT-LABEL: vand_vv: ; VLOPT: # %bb.0: -; VLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; VLOPT-NEXT: vand.vv v8, v8, v10 ; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; VLOPT-NEXT: vand.vv v8, v8, v10 ; VLOPT-NEXT: vadd.vv v8, v8, v10 ; VLOPT-NEXT: ret %1 = call @llvm.riscv.vand.nxv4i32.nxv4i32( poison, %a, %b, iXLen -1) @@ -199,9 +197,8 @@ define @vand_vx( %a, i32 %b, iXLen %vl) { ; ; VLOPT-LABEL: vand_vx: ; VLOPT: # %bb.0: -; VLOPT-NEXT: vsetvli a2, zero, e32, m2, ta, ma -; VLOPT-NEXT: vand.vx v10, v8, a0 ; VLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma +; VLOPT-NEXT: vand.vx v10, v8, a0 ; VLOPT-NEXT: vadd.vv v8, v10, v8 ; VLOPT-NEXT: ret %1 = call @llvm.riscv.vand.nxv4i32.i32( poison, %a, i32 %b, iXLen -1) @@ -220,9 +217,8 @@ define @vor_vi( %a, iXLen %vl) { ; ; VLOPT-LABEL: vor_vi: ; VLOPT: # %bb.0: -; VLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; VLOPT-NEXT: vor.vi v10, v8, 5 ; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; VLOPT-NEXT: vor.vi v10, v8, 5 ; VLOPT-NEXT: vadd.vv v8, v10, v8 ; VLOPT-NEXT: ret %1 = call @llvm.riscv.vor.nxv4i32.i32( poison, %a, i32 5, iXLen -1) @@ -241,9 +237,8 @@ define @vor_vv( %a, %b, ; ; VLOPT-LABEL: vor_vv: ; VLOPT: # %bb.0: -; VLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; VLOPT-NEXT: vor.vv v8, v8, v10 ; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; VLOPT-NEXT: vor.vv v8, v8, v10 ; VLOPT-NEXT: vadd.vv v8, v8, v10 ; VLOPT-NEXT: ret %1 = call @llvm.riscv.vor.nxv4i32.nxv4i32( poison, %a, %b, iXLen -1) @@ -262,9 +257,8 @@ define @vor_vx( %a, i32 %b, iXLen %vl) { ; ; VLOPT-LABEL: vor_vx: ; VLOPT: # %bb.0: -; VLOPT-NEXT: vsetvli a2, zero, e32, m2, ta, ma -; VLOPT-NEXT: vor.vx v10, v8, a0 ; VLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma +; VLOPT-NEXT: vor.vx v10, v8, a0 ; VLOPT-NEXT: vadd.vv v8, v10, v8 ; VLOPT-NEXT: ret %1 = call @llvm.riscv.vor.nxv4i32.i32( poison, %a, i32 %b, iXLen -1) @@ -283,9 +277,8 @@ define @vxor_vi( %a, iXLen %vl) { ; ; VLOPT-LABEL: vxor_vi: ; VLOPT: # %bb.0: -; VLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; VLOPT-NEXT: vxor.vi v10, v8, 5 ; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; VLOPT-NEXT: vxor.vi v10, v8, 5 ; VLOPT-NEXT: vadd.vv v8, v10, v8 ; VLOPT-NEXT: ret %1 = call @llvm.riscv.vxor.nxv4i32.i32( poison, %a, i32 5, iXLen -1) @@ -304,9 +297,8 @@ define @vxor_vv( %a, %b, ; ; VLOPT-LABEL: vxor_vv: ; VLOPT: # %bb.0: -; VLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; VLOPT-NEXT: vxor.vv v8, v8, v10 ; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; VLOPT-NEXT: vxor.vv v8, v8, v10 ; VLOPT-NEXT: vadd.vv v8, v8, v10 ; VLOPT-NEXT: ret %1 = call @llvm.riscv.vxor.nxv4i32.nxv4i32( poison, %a, %b, iXLen -1) @@ -325,9 +317,8 @@ define @vxor_vx( %a, i32 %b, iXLen %vl) { ; ; VLOPT-LABEL: vxor_vx: ; VLOPT: # %bb.0: -; VLOPT-NEXT: vsetvli a2, zero, e32, m2, ta, ma -; VLOPT-NEXT: vxor.vx v10, v8, a0 ; VLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma +; VLOPT-NEXT: vxor.vx v10, v8, a0 ; VLOPT-NEXT: vadd.vv v8, v10, v8 ; VLOPT-NEXT: ret %1 = call @llvm.riscv.vxor.nxv4i32.nxv4i32( poison, %a, i32 %b, iXLen -1) @@ -366,9 +357,8 @@ define @vsll_vv( %a, %b, ; ; VLOPT-LABEL: vsll_vv: ; VLOPT: # %bb.0: -; VLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; VLOPT-NEXT: vsll.vv v8, v8, v10 ; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; VLOPT-NEXT: vsll.vv v8, v8, v10 ; VLOPT-NEXT: vadd.vv v8, v8, v10 ; VLOPT-NEXT: ret %1 = call @llvm.riscv.vsll.nxv4i32.nxv4i32( poison, %a, %b, iXLen -1) @@ -387,9 +377,8 @@ define @vsll_vx( %a, iXLen %b, iXLen %vl) { ; ; VLOPT-LABEL: vsll_vx: ; VLOPT: # %bb.0: -; VLOPT-NEXT: vsetvli a2, zero, e32, m2, ta, ma -; VLOPT-NEXT: vsll.vx v10, v8, a0 ; VLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma +; VLOPT-NEXT: vsll.vx v10, v8, a0 ; VLOPT-NEXT: vadd.vv v8, v10, v8 ; VLOPT-NEXT: ret %1 = call @llvm.riscv.vsll.nxv4i32.nxv4i32( poison, %a, iXLen %b, iXLen -1) @@ -429,9 +418,8 @@ define @vsrl_vi( %a, iXLen %vl) { ; ; VLOPT-LABEL: vsrl_vi: ; VLOPT: # %bb.0: -; VLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; VLOPT-NEXT: vsrl.vi v10, v8, 5 ; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; VLOPT-NEXT: vsrl.vi v10, v8, 5 ; VLOPT-NEXT: vadd.vv v8, v10, v8 ; VLOPT-NEXT: ret %1 = call @llvm.riscv.vsrl.nxv4i32.nxv4i32( poison, %a, iXLen 5, iXLen -1) @@ -450,9 +438,8 @@ define @vsrl_vv( %a, %b, ; ; VLOPT-LABEL: vsrl_vv: ; VLOPT: # %bb.0: -; VLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; VLOPT-NEXT: vsrl.vv v8, v8, v10 ; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; VLOPT-NEXT: vsrl.vv v8, v8, v10 ; VLOPT-NEXT: vadd.vv v8, v8, v10 ; VLOPT-NEXT: ret %1 = call @llvm.riscv.vsrl.nxv4i32.nxv4i32( poison, %a, %b, iXLen -1) @@ -471,9 +458,8 @@ define @vsrl_vx( %a, iXLen %b, iXLen %vl) { ; ; VLOPT-LABEL: vsrl_vx: ; VLOPT: # %bb.0: -; VLOPT-NEXT: vsetvli a2, zero, e32, m2, ta, ma -; VLOPT-NEXT: vsrl.vx v10, v8, a0 ; VLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma +; VLOPT-NEXT: vsrl.vx v10, v8, a0 ; VLOPT-NEXT: vadd.vv v8, v10, v8 ; VLOPT-NEXT: ret %1 = call @llvm.riscv.vsrl.nxv4i32.nxv4i32( poison, %a, iXLen %b, iXLen -1) @@ -492,9 +478,8 @@ define @vsra_vi( %a, iXLen %vl) { ; ; VLOPT-LABEL: vsra_vi: ; VLOPT: # %bb.0: -; VLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; VLOPT-NEXT: vsra.vi v10, v8, 5 ; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; VLOPT-NEXT: vsra.vi v10, v8, 5 ; VLOPT-NEXT: vadd.vv v8, v10, v8 ; VLOPT-NEXT: ret %1 = call @llvm.riscv.vsra.nxv4i32.nxv4i32( poison, %a, iXLen 5, iXLen -1) @@ -513,9 +498,8 @@ define @vsra_vv( %a, %b, ; ; VLOPT-LABEL: vsra_vv: ; VLOPT: # %bb.0: -; VLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; VLOPT-NEXT: vsra.vv v8, v8, v10 ; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; VLOPT-NEXT: vsra.vv v8, v8, v10 ; VLOPT-NEXT: vadd.vv v8, v8, v10 ; VLOPT-NEXT: ret %1 = call @llvm.riscv.vsra.nxv4i32.nxv4i32( poison, %a, %b, iXLen -1) @@ -534,9 +518,8 @@ define @vsra_vx( %a, iXLen %b, iXLen %vl) { ; ; VLOPT-LABEL: vsra_vx: ; VLOPT: # %bb.0: -; VLOPT-NEXT: vsetvli a2, zero, e32, m2, ta, ma -; VLOPT-NEXT: vsra.vx v10, v8, a0 ; VLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma +; VLOPT-NEXT: vsra.vx v10, v8, a0 ; VLOPT-NEXT: vadd.vv v8, v10, v8 ; VLOPT-NEXT: ret %1 = call @llvm.riscv.vsra.nxv4i32.nxv4i32( poison, %a, iXLen %b, iXLen -1) @@ -1948,28 +1931,6 @@ define @vmv_v_i( %a, i32 %x, iXLen %vl) { ret %2 } -; The vmv.v.v is optimized away if we use a vadd as the user. -define @vmv_v_v( %a, i8 %b, %c, %m, iXLen %vl) { -; NOVLOPT-LABEL: vmerge_vvm: -; NOVLOPT: # %bb.0: -; NOVLOPT-NEXT: vsetvli a2, zero, e8, mf8, tu, ma -; NOVLOPT-NEXT: vmv.v.x v8, a0 -; NOVLOPT-NEXT: vsetvli zero, a1, e8, mf8, ta, ma -; NOVLOPT-NEXT: vmerge.vvm v8, v8, v9, v0 -; NOVLOPT-NEXT: ret -; -; VLOPT-LABEL: vmerge_vvm: -; VLOPT: # %bb.0: -; VLOPT-NEXT: vsetvli zero, a1, e8, mf8, tu, ma -; VLOPT-NEXT: vmv.v.x v8, a0 -; VLOPT-NEXT: vsetvli zero, zero, e8, mf8, ta, ma -; VLOPT-NEXT: vmerge.vvm v8, v8, v9, v0 -; VLOPT-NEXT: ret - %2 = call @llvm.riscv.vmv.v.x.nxv1i8( %a, i8 %b, iXLen -1) - %3 = call @llvm.riscv.vmerge.nxv1i8.nxv1i8( undef, %2, %c, %m, iXLen %vl) - ret %3 -} - define @vmv_v_x( %a, i32 %x, iXLen %vl) { ; NOVLOPT-LABEL: vmv_v_x: ; NOVLOPT: # %bb.0: @@ -1990,6 +1951,28 @@ define @vmv_v_x( %a, i32 %x, iXLen %vl) { ret %2 } +; The vmv.v.v is optimized away if we use a vadd as the user. +define @vmv_v_v( %a, %b, %c, %m, iXLen %vl) { +; NOVLOPT-LABEL: vmv_v_v: +; NOVLOPT: # %bb.0: +; NOVLOPT-NEXT: vsetvli a1, zero, e8, mf8, tu, ma +; NOVLOPT-NEXT: vmv.v.v v8, v9 +; NOVLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma +; NOVLOPT-NEXT: vmerge.vvm v8, v8, v10, v0 +; NOVLOPT-NEXT: ret +; +; VLOPT-LABEL: vmv_v_v: +; VLOPT: # %bb.0: +; VLOPT-NEXT: vsetvli zero, a0, e8, mf8, tu, ma +; VLOPT-NEXT: vmv.v.v v8, v9 +; VLOPT-NEXT: vsetvli zero, zero, e8, mf8, ta, ma +; VLOPT-NEXT: vmerge.vvm v8, v8, v10, v0 +; VLOPT-NEXT: ret + %2 = call @llvm.riscv.vmv.v.v.nxv1i8.nxv1i8( %a, %b, iXLen -1) + %3 = call @llvm.riscv.vmerge.nxv1i8.nxv1i8( undef, %2, %c, %m, iXLen %vl) + ret %3 +} + define @vwsll_vi( %a, %b, iXLen %vl) { ; NOVLOPT-LABEL: vwsll_vi: ; NOVLOPT: # %bb.0: