diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index eccda73548e87..465128099f444 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -3235,6 +3235,7 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
 
   case ISD::VP_SETCC:
   case ISD::STRICT_FSETCC:
+  case ISD::STRICT_FSETCCS:
   case ISD::SETCC:             Res = SplitVecOp_VSETCC(N); break;
   case ISD::BITCAST:           Res = SplitVecOp_BITCAST(N); break;
   case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
@@ -4236,7 +4237,8 @@ SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N) {
 }
 
 SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
-  bool isStrict = N->getOpcode() == ISD::STRICT_FSETCC;
+  unsigned Opc = N->getOpcode();
+  bool isStrict = Opc == ISD::STRICT_FSETCC || Opc == ISD::STRICT_FSETCCS;
   assert(N->getValueType(0).isVector() &&
          N->getOperand(isStrict ? 1 : 0).getValueType().isVector() &&
          "Operand types must be vectors");
@@ -4252,21 +4254,19 @@ SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
   EVT PartResVT = EVT::getVectorVT(Context, MVT::i1, PartEltCnt);
   EVT WideResVT = EVT::getVectorVT(Context, MVT::i1, PartEltCnt*2);
 
-  if (N->getOpcode() == ISD::SETCC) {
+  if (Opc == ISD::SETCC) {
     LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
     HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
-  } else if (N->getOpcode() == ISD::STRICT_FSETCC) {
-    LoRes = DAG.getNode(ISD::STRICT_FSETCC, DL,
-                        DAG.getVTList(PartResVT, N->getValueType(1)),
+  } else if (isStrict) {
+    LoRes = DAG.getNode(Opc, DL, DAG.getVTList(PartResVT, N->getValueType(1)),
                         N->getOperand(0), Lo0, Lo1, N->getOperand(3));
-    HiRes = DAG.getNode(ISD::STRICT_FSETCC, DL,
-                        DAG.getVTList(PartResVT, N->getValueType(1)),
+    HiRes = DAG.getNode(Opc, DL, DAG.getVTList(PartResVT, N->getValueType(1)),
                         N->getOperand(0), Hi0, Hi1, N->getOperand(3));
     SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
                                    LoRes.getValue(1), HiRes.getValue(1));
     ReplaceValueWith(SDValue(N, 1), NewChain);
   } else {
-    assert(N->getOpcode() == ISD::VP_SETCC && "Expected VP_SETCC opcode");
+    assert(Opc == ISD::VP_SETCC && "Expected VP_SETCC opcode");
     SDValue MaskLo, MaskHi, EVLLo, EVLHi;
     std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(3));
     std::tie(EVLLo, EVLHi) =
diff --git a/llvm/test/CodeGen/X86/vec-strict-cmp-512-skx.ll b/llvm/test/CodeGen/X86/vec-strict-cmp-512-skx.ll
index 3028b74967378..0ec33ad800912 100644
--- a/llvm/test/CodeGen/X86/vec-strict-cmp-512-skx.ll
+++ b/llvm/test/CodeGen/X86/vec-strict-cmp-512-skx.ll
@@ -34,7 +34,34 @@ define <8 x i32> @test_v8f64_oeq_q(<8 x i32> %a, <8 x i32> %b, <8 x double> %f1,
   ret <8 x i32> %res
 }
 
+define <16 x i32> @test_v16f64_ogt(<16 x i32> %a, <16 x i32> %b, <16 x double> %f1, <16 x double> %f2) #0 {
+; SKX-LABEL: test_v16f64_ogt
+; SKX:       # %bb.0:
+; SKX-NEXT:  pushq	%rbp
+; SKX-NEXT:  movq	%rsp, %rbp
+; SKX-NEXT:  andq	$-32, %rsp
+; SKX-NEXT:  subq	$32, %rsp
+; SKX-NEXT:  vcmpgtpd	80(%rbp), %ymm6, %k0
+; SKX-NEXT:  vcmpgtpd	112(%rbp), %ymm7, %k1
+; SKX-NEXT:  kshiftlb	$4, %k1, %k1
+; SKX-NEXT:  korb	%k1, %k0, %k1
+; SKX-NEXT:  vcmpgtpd	16(%rbp), %ymm4, %k0
+; SKX-NEXT:  vcmpgtpd	48(%rbp), %ymm5, %k2
+; SKX-NEXT:  kshiftlb	$4, %k2, %k2
+; SKX-NEXT:  korb	%k2, %k0, %k2
+; SKX-NEXT:  vpblendmd	%ymm0, %ymm2, %ymm0 {%k2}
+; SKX-NEXT:  vpblendmd	%ymm1, %ymm3, %ymm1 {%k1}
+; SKX-NEXT:  movq	%rbp, %rsp
+; SKX-NEXT:  popq	%rbp
+; SKX-NEXT:  retq
+  %cond = tail call <16 x i1> @llvm.experimental.constrained.fcmps.v16f64(
+    <16 x double> %f1, <16 x double> %f2, metadata !"ogt", metadata !"fpexcept.maytrap")
+  %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+  ret <16 x i32> %res
+}
+
 declare <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float>, <16 x float>, metadata, metadata)
 declare <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double>, <8 x double>, metadata, metadata)
+declare <16 x i1> @llvm.experimental.constrained.fcmps.v16f64(<16 x double>, <16 x double>, metadata, metadata)
 
 attributes #0 = { nounwind strictfp "min-legal-vector-width"="0" }