From c97b9d7da3bf55d949c4248a296a67baba0657df Mon Sep 17 00:00:00 2001 From: Akshat Oke Date: Fri, 27 Sep 2024 08:57:33 +0000 Subject: [PATCH 1/9] [MIR] Serialize virtual register flags --- .../include/llvm/CodeGen/MIRParser/MIParser.h | 3 +++ llvm/include/llvm/CodeGen/MIRYamlMapping.h | 3 +++ .../include/llvm/CodeGen/TargetRegisterInfo.h | 9 +++++++ llvm/lib/CodeGen/MIRParser/MIParser.cpp | 11 ++++++++ llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 9 +++++++ llvm/lib/CodeGen/MIRPrinter.cpp | 27 ++++++++++++++----- 6 files changed, 55 insertions(+), 7 deletions(-) diff --git a/llvm/include/llvm/CodeGen/MIRParser/MIParser.h b/llvm/include/llvm/CodeGen/MIRParser/MIParser.h index 7fd9d99ded699..a1a48f2fb02a8 100644 --- a/llvm/include/llvm/CodeGen/MIRParser/MIParser.h +++ b/llvm/include/llvm/CodeGen/MIRParser/MIParser.h @@ -47,6 +47,7 @@ struct VRegInfo { } D; Register VReg; Register PreferredReg; + std::vector<::uint8_t> Flags; }; using Name2RegClassMap = StringMap; @@ -150,6 +151,8 @@ struct PerTargetMIParsingState { /// Return null if the name isn't a register bank. const RegisterBank *getRegBank(StringRef Name); + bool getVRegFlagValue(StringRef FlagName, uint8_t& FlagValue) const; + PerTargetMIParsingState(const TargetSubtargetInfo &STI) : Subtarget(STI) { initNames2RegClasses(); diff --git a/llvm/include/llvm/CodeGen/MIRYamlMapping.h b/llvm/include/llvm/CodeGen/MIRYamlMapping.h index c5bf6971df453..09a6ca936fe1f 100644 --- a/llvm/include/llvm/CodeGen/MIRYamlMapping.h +++ b/llvm/include/llvm/CodeGen/MIRYamlMapping.h @@ -191,6 +191,7 @@ struct VirtualRegisterDefinition { UnsignedValue ID; StringValue Class; StringValue PreferredRegister; + std::vector RegisterFlags; // TODO: Serialize the target specific register hints. @@ -206,6 +207,8 @@ template <> struct MappingTraits { YamlIO.mapRequired("class", Reg.Class); YamlIO.mapOptional("preferred-register", Reg.PreferredRegister, StringValue()); // Don't print out when it's empty. + YamlIO.mapOptional("flags", Reg.RegisterFlags, + std::vector()); } static const bool flow = true; diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h index 9ea0fba1144b1..6ec38ebb4f886 100644 --- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h +++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h @@ -1213,6 +1213,15 @@ class TargetRegisterInfo : public MCRegisterInfo { virtual bool isNonallocatableRegisterCalleeSave(MCRegister Reg) const { return false; } + + virtual std::pair getVRegFlagValue(StringRef Name) const { + return {false, 0}; + } + + virtual SmallVector + getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const { + return {}; + } }; //===----------------------------------------------------------------------===// diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp index 74f38e886a6b9..f27fea1f748d9 100644 --- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp @@ -127,6 +127,16 @@ bool PerTargetMIParsingState::getRegisterByName(StringRef RegName, return false; } +bool PerTargetMIParsingState::getVRegFlagValue(StringRef FlagName, uint8_t& FlagValue) const { + const auto *TRI = Subtarget.getRegisterInfo(); + assert(TRI && "Expected target register info"); + auto [HasVReg, FV] = TRI->getVRegFlagValue(FlagName); + if(!HasVReg) + return true; + FlagValue = FV; + return false; +} + void PerTargetMIParsingState::initNames2InstrOpCodes() { if (!Names2InstrOpCodes.empty()) return; @@ -1776,6 +1786,7 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest, MRI.setRegClassOrRegBank(Reg, static_cast(nullptr)); MRI.setType(Reg, Ty); + MRI.noteNewVirtualRegister(Reg); } } } else if (consumeIfPresent(MIToken::lparen)) { diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp index 30b1a717caaab..1f995c962a489 100644 --- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp @@ -696,6 +696,15 @@ bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS, VReg.PreferredRegister.Value, Error)) return error(Error, VReg.PreferredRegister.SourceRange); } + + for(const auto &FlagStringValue: VReg.RegisterFlags) { + uint8_t FlagValue; + if(Target->getVRegFlagValue(FlagStringValue.Value, FlagValue)) + return error(FlagStringValue.SourceRange.Start, + Twine("use of undefined register flag '") + + FlagStringValue.Value + "'"); + Info.Flags.push_back(FlagValue); + } } // Parse the liveins. diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp index d52c1d831267f..8791e41ad613c 100644 --- a/llvm/lib/CodeGen/MIRPrinter.cpp +++ b/llvm/lib/CodeGen/MIRPrinter.cpp @@ -113,7 +113,8 @@ class MIRPrinter { void print(const MachineFunction &MF); - void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo, + void convert(yaml::MachineFunction &YamlMF, const MachineFunction &MF, + const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI); void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI, const MachineFrameInfo &MFI); @@ -231,7 +232,7 @@ void MIRPrinter::print(const MachineFunction &MF) { YamlMF.NoVRegs = MF.getProperties().hasProperty( MachineFunctionProperties::Property::NoVRegs); - convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo()); + convert(YamlMF, MF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo()); MachineModuleSlotTracker MST(MMI, &MF); MST.incorporateFunction(MF.getFunction()); convert(MST, YamlMF.FrameInfo, MF.getFrameInfo()); @@ -316,10 +317,21 @@ printStackObjectDbgInfo(const MachineFunction::VariableDbgInfo &DebugVar, } } -void MIRPrinter::convert(yaml::MachineFunction &MF, +static void printRegFlags(Register Reg, + std::vector &RegisterFlags, + const MachineFunction &MF, + const TargetRegisterInfo *TRI) { + SmallVector FlagValues = TRI->getVRegFlagsOfReg(Reg, MF); + for (auto &Flag : FlagValues) { + RegisterFlags.push_back(yaml::FlowStringValue(Flag)); + } +} + +void MIRPrinter::convert(yaml::MachineFunction &YamlMF, + const MachineFunction &MF, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI) { - MF.TracksRegLiveness = RegInfo.tracksLiveness(); + YamlMF.TracksRegLiveness = RegInfo.tracksLiveness(); // Print the virtual register definitions. for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) { @@ -332,7 +344,8 @@ void MIRPrinter::convert(yaml::MachineFunction &MF, Register PreferredReg = RegInfo.getSimpleHint(Reg); if (PreferredReg) printRegMIR(PreferredReg, VReg.PreferredRegister, TRI); - MF.VirtualRegisters.push_back(VReg); + printRegFlags(Reg, VReg.RegisterFlags, MF, TRI); + YamlMF.VirtualRegisters.push_back(VReg); } // Print the live ins. @@ -341,7 +354,7 @@ void MIRPrinter::convert(yaml::MachineFunction &MF, printRegMIR(LI.first, LiveIn.Register, TRI); if (LI.second) printRegMIR(LI.second, LiveIn.VirtualRegister, TRI); - MF.LiveIns.push_back(LiveIn); + YamlMF.LiveIns.push_back(LiveIn); } // Prints the callee saved registers. @@ -353,7 +366,7 @@ void MIRPrinter::convert(yaml::MachineFunction &MF, printRegMIR(*I, Reg, TRI); CalleeSavedRegisters.push_back(Reg); } - MF.CalleeSavedRegisters = CalleeSavedRegisters; + YamlMF.CalleeSavedRegisters = CalleeSavedRegisters; } } From 632b3d705b52a1e35cd1fe6cfcbfc5a9c50625c4 Mon Sep 17 00:00:00 2001 From: Akshat Oke Date: Fri, 27 Sep 2024 09:26:01 +0000 Subject: [PATCH 2/9] Update tests --- llvm/test/CodeGen/AMDGPU/limit-coalesce.mir | 14 ++-- ...cted-named-register-in-allocation-hint.mir | 4 +- .../CodeGen/MIR/X86/generic-instr-type.mir | 10 +-- .../MIR/X86/register-operand-class.mir | 10 +-- llvm/test/CodeGen/MIR/X86/roundtrip.mir | 4 +- .../X86/simple-register-allocation-hints.mir | 6 +- .../CodeGen/MIR/X86/virtual-registers.mir | 12 ++-- .../X86/GlobalISel/legalize-mul-v128.mir | 18 ++--- .../X86/GlobalISel/legalize-mul-v256.mir | 18 ++--- .../X86/GlobalISel/legalize-mul-v512.mir | 18 ++--- .../X86/GlobalISel/regbankselect-AVX2.mir | 20 +++--- .../X86/GlobalISel/regbankselect-AVX512.mir | 20 +++--- .../X86/GlobalISel/regbankselect-X32.mir | 10 +-- .../CodeGen/X86/GlobalISel/select-GV-32.mir | 12 ++-- .../CodeGen/X86/GlobalISel/select-GV-64.mir | 8 +-- .../X86/GlobalISel/select-add-v128.mir | 72 +++++++++---------- .../X86/GlobalISel/select-add-v256.mir | 72 +++++++++---------- .../CodeGen/X86/GlobalISel/select-copy.mir | 38 +++++----- .../X86/GlobalISel/select-extract-vec256.mir | 16 ++--- .../X86/GlobalISel/select-extract-vec512.mir | 16 ++--- .../CodeGen/X86/GlobalISel/select-inc.mir | 8 +-- .../X86/GlobalISel/select-memop-v256.mir | 24 +++---- .../X86/GlobalISel/x86-legalize-GV.mir | 2 +- .../X86/GlobalISel/x86_64-legalize-GV.mir | 2 +- .../llvm-reduce/mir/preserve-reg-hints.mir | 10 +-- 25 files changed, 222 insertions(+), 222 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/limit-coalesce.mir b/llvm/test/CodeGen/AMDGPU/limit-coalesce.mir index b9105418a588c..ca774825f4dde 100644 --- a/llvm/test/CodeGen/AMDGPU/limit-coalesce.mir +++ b/llvm/test/CodeGen/AMDGPU/limit-coalesce.mir @@ -2,13 +2,13 @@ # Check that coalescer does not create wider register tuple than in source -# CHECK: - { id: 2, class: vreg_64, preferred-register: '' } -# CHECK: - { id: 3, class: vreg_64, preferred-register: '' } -# CHECK: - { id: 4, class: vreg_64, preferred-register: '' } -# CHECK: - { id: 5, class: vreg_96, preferred-register: '' } -# CHECK: - { id: 6, class: vreg_96, preferred-register: '' } -# CHECK: - { id: 7, class: vreg_128, preferred-register: '' } -# CHECK: - { id: 8, class: vreg_128, preferred-register: '' } +# CHECK: - { id: 2, class: vreg_64, preferred-register: '', flags: [ ] } +# CHECK: - { id: 3, class: vreg_64, preferred-register: '', flags: [ ] } +# CHECK: - { id: 4, class: vreg_64, preferred-register: '', flags: [ ] } +# CHECK: - { id: 5, class: vreg_96, preferred-register: '', flags: [ ] } +# CHECK: - { id: 6, class: vreg_96, preferred-register: '', flags: [ ] } +# CHECK: - { id: 7, class: vreg_128, preferred-register: '', flags: [ ] } +# CHECK: - { id: 8, class: vreg_128, preferred-register: '', flags: [ ] } # No more registers shall be defined # CHECK-NEXT: liveins: # CHECK: FLAT_STORE_DWORDX2 $vgpr0_vgpr1, %4, diff --git a/llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir b/llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir index 7ed390570adc7..03f2ec4d6cd3f 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir @@ -14,8 +14,8 @@ name: test tracksRegLiveness: true registers: - { id: 0, class: gr32 } - # CHECK: - { id: 1, class: gr32, preferred-register: '%0' } - # CHECK: - { id: 2, class: gr32, preferred-register: '$edi' } + # CHECK: - { id: 1, class: gr32, preferred-register: '%0', flags: [ ] } + # CHECK: - { id: 2, class: gr32, preferred-register: '$edi', flags: [ ] } - { id: 1, class: gr32, preferred-register: '%0' } - { id: 2, class: gr32, preferred-register: '$edi' } body: | diff --git a/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir b/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir index 710a18ac3aeff..7514cdab0ab11 100644 --- a/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir +++ b/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir @@ -18,11 +18,11 @@ --- name: test_vregs # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: _, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: _, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: _, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: _, preferred-register: '' } -# CHECK-NEXT: - { id: 4, class: _, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] } +# CHECK-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] } +# CHECK-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] } +# CHECK-NEXT: - { id: 3, class: _, preferred-register: '', flags: [ ] } +# CHECK-NEXT: - { id: 4, class: _, preferred-register: '', flags: [ ] } registers: - { id: 0, class: _ } - { id: 1, class: _ } diff --git a/llvm/test/CodeGen/MIR/X86/register-operand-class.mir b/llvm/test/CodeGen/MIR/X86/register-operand-class.mir index f62d7294eabc1..521722d9f24c5 100644 --- a/llvm/test/CodeGen/MIR/X86/register-operand-class.mir +++ b/llvm/test/CodeGen/MIR/X86/register-operand-class.mir @@ -6,11 +6,11 @@ --- # CHECK-LABEL: name: func # CHECK: registers: -# CHECK: - { id: 0, class: gr32, preferred-register: '' } -# CHECK: - { id: 1, class: gr64, preferred-register: '' } -# CHECK: - { id: 2, class: gr32, preferred-register: '' } -# CHECK: - { id: 3, class: gr16, preferred-register: '' } -# CHECK: - { id: 4, class: _, preferred-register: '' } +# CHECK: - { id: 0, class: gr32, preferred-register: '', flags: [ ] } +# CHECK: - { id: 1, class: gr64, preferred-register: '', flags: [ ] } +# CHECK: - { id: 2, class: gr32, preferred-register: '', flags: [ ] } +# CHECK: - { id: 3, class: gr16, preferred-register: '', flags: [ ] } +# CHECK: - { id: 4, class: _, preferred-register: '', flags: [ ] } name: func body: | bb.0: diff --git a/llvm/test/CodeGen/MIR/X86/roundtrip.mir b/llvm/test/CodeGen/MIR/X86/roundtrip.mir index 46f08ad1a214d..6124113a0dd88 100644 --- a/llvm/test/CodeGen/MIR/X86/roundtrip.mir +++ b/llvm/test/CodeGen/MIR/X86/roundtrip.mir @@ -2,8 +2,8 @@ --- # CHECK-LABEL: name: func0 # CHECK: registers: -# CHECK: - { id: 0, class: gr32, preferred-register: '' } -# CHECK: - { id: 1, class: gr32, preferred-register: '' } +# CHECK: - { id: 0, class: gr32, preferred-register: '', flags: [ ] } +# CHECK: - { id: 1, class: gr32, preferred-register: '', flags: [ ] } # CHECK: body: | # CHECK: bb.0: # CHECK: %0:gr32 = MOV32r0 implicit-def $eflags diff --git a/llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir b/llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir index 84d298dbd4070..aacf66c98cf5d 100644 --- a/llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir +++ b/llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir @@ -15,9 +15,9 @@ name: test tracksRegLiveness: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '$esi' } -# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '$edi' } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '', flags: [ ] } +# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '$esi', flags: [ ] } +# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '$edi', flags: [ ] } registers: - { id: 0, class: gr32 } - { id: 1, class: gr32, preferred-register: '$esi' } diff --git a/llvm/test/CodeGen/MIR/X86/virtual-registers.mir b/llvm/test/CodeGen/MIR/X86/virtual-registers.mir index e317746e08a18..819f65638b67d 100644 --- a/llvm/test/CodeGen/MIR/X86/virtual-registers.mir +++ b/llvm/test/CodeGen/MIR/X86/virtual-registers.mir @@ -33,9 +33,9 @@ name: bar tracksRegLiveness: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '', flags: [ ] } +# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '', flags: [ ] } +# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '', flags: [ ] } registers: - { id: 0, class: gr32 } - { id: 1, class: gr32 } @@ -67,9 +67,9 @@ name: foo tracksRegLiveness: true # CHECK: name: foo # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '', flags: [ ] } +# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '', flags: [ ] } +# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '', flags: [ ] } registers: - { id: 2, class: gr32 } - { id: 0, class: gr32 } diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir index 3b8455684f33d..881ceac1d1f7f 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir @@ -26,9 +26,9 @@ alignment: 16 legalized: false regBankSelected: false # ALL: registers: -# ALL-NEXT: - { id: 0, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] } +# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] } +# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -56,9 +56,9 @@ alignment: 16 legalized: false regBankSelected: false # ALL: registers: -# ALL-NEXT: - { id: 0, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] } +# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] } +# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -86,9 +86,9 @@ alignment: 16 legalized: false regBankSelected: false # ALL: registers: -# ALL-NEXT: - { id: 0, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] } +# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] } +# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] } registers: - { id: 0, class: _ } - { id: 1, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir index 4965b069715a1..c2800bef9713d 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir @@ -26,9 +26,9 @@ alignment: 16 legalized: false regBankSelected: false # ALL: registers: -# ALL-NEXT: - { id: 0, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] } +# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] } +# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -56,9 +56,9 @@ alignment: 16 legalized: false regBankSelected: false # ALL: registers: -# ALL-NEXT: - { id: 0, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] } +# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] } +# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -86,9 +86,9 @@ alignment: 16 legalized: false regBankSelected: false # ALL: registers: -# ALL-NEXT: - { id: 0, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] } +# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] } +# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] } registers: - { id: 0, class: _ } - { id: 1, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir index 77a94581b66fd..e45818af22a35 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir @@ -28,9 +28,9 @@ alignment: 16 legalized: false regBankSelected: false # ALL: registers: -# ALL-NEXT: - { id: 0, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] } +# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] } +# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -58,9 +58,9 @@ alignment: 16 legalized: false regBankSelected: false # ALL: registers: -# ALL-NEXT: - { id: 0, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] } +# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] } +# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -88,9 +88,9 @@ alignment: 16 legalized: false regBankSelected: false # ALL: registers: -# ALL-NEXT: - { id: 0, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: _, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] } +# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] } +# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] } registers: - { id: 0, class: _ } - { id: 1, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir index 1d280e9e4bd11..28c4eaea38841 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir @@ -33,8 +33,8 @@ selected: false tracksRegLiveness: true # CHECK-LABEL: name: test_mul_vec256 # CHECK: registers: -# CHECK: - { id: 0, class: vecr, preferred-register: '' } -# CHECK: - { id: 1, class: vecr, preferred-register: '' } +# CHECK: - { id: 0, class: vecr, preferred-register: '', flags: [ ] } +# CHECK: - { id: 1, class: vecr, preferred-register: '', flags: [ ] } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -56,8 +56,8 @@ selected: false tracksRegLiveness: true # CHECK-LABEL: name: test_add_vec256 # CHECK: registers: -# CHECK: - { id: 0, class: vecr, preferred-register: '' } -# CHECK: - { id: 1, class: vecr, preferred-register: '' } +# CHECK: - { id: 0, class: vecr, preferred-register: '', flags: [ ] } +# CHECK: - { id: 1, class: vecr, preferred-register: '', flags: [ ] } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -79,8 +79,8 @@ selected: false tracksRegLiveness: true # CHECK-LABEL: name: test_sub_vec256 # CHECK: registers: -# CHECK: - { id: 0, class: vecr, preferred-register: '' } -# CHECK: - { id: 1, class: vecr, preferred-register: '' } +# CHECK: - { id: 0, class: vecr, preferred-register: '', flags: [ ] } +# CHECK: - { id: 1, class: vecr, preferred-register: '', flags: [ ] } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -100,8 +100,8 @@ alignment: 16 legalized: true regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '', flags: [ ] } +# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '', flags: [ ] } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -122,8 +122,8 @@ alignment: 16 legalized: true regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '', flags: [ ] } +# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] } registers: - { id: 0, class: _ } - { id: 1, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir index 2f8827c7ff906..4a19a040b0ce8 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir @@ -33,8 +33,8 @@ alignment: 16 legalized: true regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '', flags: [ ] } +# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '', flags: [ ] } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -53,8 +53,8 @@ alignment: 16 legalized: true regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '', flags: [ ] } +# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '', flags: [ ] } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -73,8 +73,8 @@ alignment: 16 legalized: true regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '', flags: [ ] } +# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '', flags: [ ] } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -93,8 +93,8 @@ alignment: 16 legalized: true regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '', flags: [ ] } +# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '', flags: [ ] } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -115,8 +115,8 @@ alignment: 16 legalized: true regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '', flags: [ ] } +# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] } registers: - { id: 0, class: _ } - { id: 1, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir index c69345ccf5a2a..8eac3eaf36145 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir @@ -14,11 +14,11 @@ alignment: 16 legalized: true regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 4, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '', flags: [ ] } +# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] } +# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '', flags: [ ] } +# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '', flags: [ ] } +# CHECK-NEXT: - { id: 4, class: gpr, preferred-register: '', flags: [ ] } registers: - { id: 0, class: _ } - { id: 1, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-GV-32.mir b/llvm/test/CodeGen/X86/GlobalISel/select-GV-32.mir index 4ba8606df5dfc..43c4105c883e1 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-GV-32.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-GV-32.mir @@ -25,12 +25,12 @@ alignment: 16 legalized: true regBankSelected: true # X32: registers: -# X32-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# X32-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# X32-NEXT: - { id: 0, class: gr32, preferred-register: '', flags: [ ] } +# X32-NEXT: - { id: 1, class: gr32, preferred-register: '', flags: [ ] } # # X32ABI: registers: -# X32ABI-NEXT: - { id: 0, class: low32_addr_access, preferred-register: '' } -# X32ABI-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# X32ABI-NEXT: - { id: 0, class: low32_addr_access, preferred-register: '', flags: [ ] } +# X32ABI-NEXT: - { id: 1, class: gr32, preferred-register: '', flags: [ ] } registers: - { id: 0, class: gpr, preferred-register: '' } - { id: 1, class: gpr, preferred-register: '' } @@ -60,8 +60,8 @@ alignment: 16 legalized: true regBankSelected: true # X32ALL: registers: -# X32ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# X32ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# X32ALL-NEXT: - { id: 0, class: gr32, preferred-register: '', flags: [ ] } +# X32ALL-NEXT: - { id: 1, class: gr32, preferred-register: '', flags: [ ] } registers: - { id: 0, class: gpr, preferred-register: '' } - { id: 1, class: gpr, preferred-register: '' } diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-GV-64.mir b/llvm/test/CodeGen/X86/GlobalISel/select-GV-64.mir index 4a1f63c987955..d292bbfcaa98b 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-GV-64.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-GV-64.mir @@ -25,8 +25,8 @@ alignment: 16 legalized: true regBankSelected: true # X64ALL: registers: -# X64ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' } -# X64ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' } +# X64ALL-NEXT: - { id: 0, class: gr64, preferred-register: '', flags: [ ] } +# X64ALL-NEXT: - { id: 1, class: gr64, preferred-register: '', flags: [ ] } # registers: - { id: 0, class: gpr, preferred-register: '' } @@ -58,8 +58,8 @@ alignment: 16 legalized: true regBankSelected: true # X64ALL: registers: -# X64ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# X64ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' } +# X64ALL-NEXT: - { id: 0, class: gr32, preferred-register: '', flags: [ ] } +# X64ALL-NEXT: - { id: 1, class: gr64, preferred-register: '', flags: [ ] } # registers: - { id: 0, class: gpr, preferred-register: '' } diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-add-v128.mir b/llvm/test/CodeGen/X86/GlobalISel/select-add-v128.mir index 987f67bad15b3..32898be2e6f5e 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-add-v128.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-add-v128.mir @@ -32,19 +32,19 @@ alignment: 16 legalized: true regBankSelected: true # NOVL: registers: -# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' } -# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' } -# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '', flags: [ ] } +# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '', flags: [ ] } +# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '', flags: [ ] } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' } -# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' } -# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' } +# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '', flags: [ ] } +# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '', flags: [ ] } +# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '', flags: [ ] } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '', flags: [ ] } +# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] } +# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '', flags: [ ] } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -74,19 +74,19 @@ alignment: 16 legalized: true regBankSelected: true # NOVL: registers: -# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' } -# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' } -# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '', flags: [ ] } +# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '', flags: [ ] } +# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '', flags: [ ] } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' } -# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' } -# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' } +# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '', flags: [ ] } +# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '', flags: [ ] } +# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '', flags: [ ] } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '', flags: [ ] } +# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] } +# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '', flags: [ ] } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -116,19 +116,19 @@ alignment: 16 legalized: true regBankSelected: true # NOVL: registers: -# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' } -# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' } -# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '', flags: [ ] } +# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '', flags: [ ] } +# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '', flags: [ ] } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '', flags: [ ] } +# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] } +# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '', flags: [ ] } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '', flags: [ ] } +# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] } +# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '', flags: [ ] } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -158,19 +158,19 @@ alignment: 16 legalized: true regBankSelected: true # NOVL: registers: -# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' } -# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' } -# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '', flags: [ ] } +# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '', flags: [ ] } +# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '', flags: [ ] } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '', flags: [ ] } +# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] } +# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '', flags: [ ] } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '', flags: [ ] } +# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] } +# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '', flags: [ ] } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir b/llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir index 3ee959294413d..742cc4378e3eb 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir @@ -30,19 +30,19 @@ alignment: 16 legalized: true regBankSelected: true # AVX2: registers: -# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' } -# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' } -# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' } +# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] } +# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '', flags: [ ] } +# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '', flags: [ ] } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: '' } -# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: '' } -# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: '' } +# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] } +# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: '', flags: [ ] } +# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: '', flags: [ ] } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] } +# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] } +# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '', flags: [ ] } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -70,19 +70,19 @@ alignment: 16 legalized: true regBankSelected: true # AVX2: registers: -# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' } -# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' } -# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' } +# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] } +# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '', flags: [ ] } +# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '', flags: [ ] } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: '' } -# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: '' } -# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: '' } +# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] } +# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: '', flags: [ ] } +# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: '', flags: [ ] } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] } +# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] } +# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '', flags: [ ] } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -110,19 +110,19 @@ alignment: 16 legalized: true regBankSelected: true # AVX2: registers: -# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' } -# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' } -# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' } +# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] } +# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '', flags: [ ] } +# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '', flags: [ ] } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] } +# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] } +# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '', flags: [ ] } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] } +# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] } +# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '', flags: [ ] } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -150,19 +150,19 @@ alignment: 16 legalized: true regBankSelected: true # AVX2: registers: -# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' } -# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' } -# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' } +# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] } +# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '', flags: [ ] } +# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '', flags: [ ] } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] } +# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] } +# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '', flags: [ ] } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } -# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] } +# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] } +# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '', flags: [ ] } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-copy.mir b/llvm/test/CodeGen/X86/GlobalISel/select-copy.mir index 72a6ed15f63b5..41e1b5bf22bf1 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-copy.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-copy.mir @@ -35,8 +35,8 @@ alignment: 16 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '', flags: [ ] } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '', flags: [ ] } registers: - { id: 0, class: gpr, preferred-register: '' } - { id: 1, class: gpr, preferred-register: '' } @@ -61,8 +61,8 @@ alignment: 16 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '', flags: [ ] } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '', flags: [ ] } registers: - { id: 0, class: gpr, preferred-register: '' } - { id: 1, class: gpr, preferred-register: '' } @@ -87,10 +87,10 @@ alignment: 16 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr16[[ABCD:(_abcd)?]], preferred-register: '' } -# X32-NEXT: - { id: 1, class: gr8_abcd_l, preferred-register: '' } -# X64-NEXT: - { id: 1, class: gr8, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr16[[ABCD:(_abcd)?]], preferred-register: '', flags: [ ] } +# X32-NEXT: - { id: 1, class: gr8_abcd_l, preferred-register: '', flags: [ ] } +# X64-NEXT: - { id: 1, class: gr8, preferred-register: '', flags: [ ] } +# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '', flags: [ ] } registers: - { id: 0, class: gpr, preferred-register: '' } - { id: 1, class: gpr, preferred-register: '' } @@ -120,9 +120,9 @@ alignment: 16 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr16, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '', flags: [ ] } +# ALL-NEXT: - { id: 1, class: gr16, preferred-register: '', flags: [ ] } +# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '', flags: [ ] } registers: - { id: 0, class: gpr, preferred-register: '' } - { id: 1, class: gpr, preferred-register: '' } @@ -150,10 +150,10 @@ alignment: 16 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr32[[ABCD:(_abcd)?]], preferred-register: '' } -# X32-NEXT: - { id: 1, class: gr8_abcd_l, preferred-register: '' } -# X64-NEXT: - { id: 1, class: gr8, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr32[[ABCD:(_abcd)?]], preferred-register: '', flags: [ ] } +# X32-NEXT: - { id: 1, class: gr8_abcd_l, preferred-register: '', flags: [ ] } +# X64-NEXT: - { id: 1, class: gr8, preferred-register: '', flags: [ ] } +# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '', flags: [ ] } registers: - { id: 0, class: gpr, preferred-register: '' } - { id: 1, class: gpr, preferred-register: '' } @@ -183,10 +183,10 @@ alignment: 16 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr16, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: low32_addr_access_rbp, preferred-register: '' } -# ALL-NEXT: - { id: 3, class: low32_addr_access_rbp, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '', flags: [ ] } +# ALL-NEXT: - { id: 1, class: gr16, preferred-register: '', flags: [ ] } +# ALL-NEXT: - { id: 2, class: low32_addr_access_rbp, preferred-register: '', flags: [ ] } +# ALL-NEXT: - { id: 3, class: low32_addr_access_rbp, preferred-register: '', flags: [ ] } registers: - { id: 0, class: gpr, preferred-register: '' } - { id: 1, class: gpr, preferred-register: '' } diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec256.mir b/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec256.mir index 73af03b34ec77..301d63b7f3643 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec256.mir @@ -18,12 +18,12 @@ alignment: 16 legalized: true regBankSelected: true # AVX: registers: -# AVX-NEXT: - { id: 0, class: vr256, preferred-register: '' } -# AVX-NEXT: - { id: 1, class: vr128, preferred-register: '' } +# AVX-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] } +# AVX-NEXT: - { id: 1, class: vr128, preferred-register: '', flags: [ ] } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] } +# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -50,12 +50,12 @@ alignment: 16 legalized: true regBankSelected: true # AVX: registers: -# AVX-NEXT: - { id: 0, class: vr256, preferred-register: '' } -# AVX-NEXT: - { id: 1, class: vr128, preferred-register: '' } +# AVX-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] } +# AVX-NEXT: - { id: 1, class: vr128, preferred-register: '', flags: [ ] } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } -# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] } +# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec512.mir b/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec512.mir index 5ddf58e645557..cff8560a4ba45 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec512.mir @@ -27,8 +27,8 @@ alignment: 16 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '', flags: [ ] } +# ALL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -53,8 +53,8 @@ alignment: 16 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '', flags: [ ] } +# ALL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -79,8 +79,8 @@ alignment: 16 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '', flags: [ ] } +# ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -105,8 +105,8 @@ alignment: 16 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '', flags: [ ] } +# ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-inc.mir b/llvm/test/CodeGen/X86/GlobalISel/select-inc.mir index 45e2b47176b97..b834155d49f64 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-inc.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-inc.mir @@ -13,10 +13,10 @@ name: test_add_i8 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' } -# INC-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# ADD-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gr8, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '', flags: [ ] } +# INC-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] } +# ADD-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] } +# ALL-NEXT: - { id: 2, class: gr8, preferred-register: '', flags: [ ] } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-memop-v256.mir b/llvm/test/CodeGen/X86/GlobalISel/select-memop-v256.mir index f24a82899c62e..86a83c417d63e 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-memop-v256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-memop-v256.mir @@ -33,12 +33,12 @@ alignment: 16 legalized: true regBankSelected: true # NO_AVX512F: registers: -# NO_AVX512F-NEXT: - { id: 0, class: gr64, preferred-register: '' } -# NO_AVX512F-NEXT: - { id: 1, class: vr256, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 0, class: gr64, preferred-register: '', flags: [ ] } +# NO_AVX512F-NEXT: - { id: 1, class: vr256, preferred-register: '', flags: [ ] } # # AVX512ALL: registers: -# AVX512ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 0, class: gr64, preferred-register: '', flags: [ ] } +# AVX512ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] } registers: - { id: 0, class: gpr } - { id: 1, class: vecr } @@ -106,12 +106,12 @@ alignment: 16 legalized: true regBankSelected: true # NO_AVX512F: registers: -# NO_AVX512F-NEXT: - { id: 0, class: vr256, preferred-register: '' } -# NO_AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] } +# NO_AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '', flags: [ ] } # # AVX512ALL: registers: -# AVX512ALL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] } +# AVX512ALL-NEXT: - { id: 1, class: gr64, preferred-register: '', flags: [ ] } registers: - { id: 0, class: vecr } - { id: 1, class: gpr } @@ -146,12 +146,12 @@ alignment: 16 legalized: true regBankSelected: true # NO_AVX512F: registers: -# NO_AVX512F-NEXT: - { id: 0, class: vr256, preferred-register: '' } -# NO_AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] } +# NO_AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '', flags: [ ] } # # AVX512ALL: registers: -# AVX512ALL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] } +# AVX512ALL-NEXT: - { id: 1, class: gr64, preferred-register: '', flags: [ ] } registers: - { id: 0, class: vecr } - { id: 1, class: gpr } diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-GV.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-GV.mir index 61f9eb9a72874..50f6fbd59cd99 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-GV.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-GV.mir @@ -15,7 +15,7 @@ alignment: 16 legalized: false regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: _, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] } registers: - { id: 0, class: _, preferred-register: '' } # CHECK: %0:_(p0) = G_GLOBAL_VALUE @g_int diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-GV.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-GV.mir index a2cf55dc2ba54..e7c5d9b367941 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-GV.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-GV.mir @@ -15,7 +15,7 @@ alignment: 16 legalized: false regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: _, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] } registers: - { id: 0, class: _, preferred-register: '' } # CHECK: %0:_(p0) = G_GLOBAL_VALUE @g_int diff --git a/llvm/test/tools/llvm-reduce/mir/preserve-reg-hints.mir b/llvm/test/tools/llvm-reduce/mir/preserve-reg-hints.mir index ae55990c1ad87..8ba07c31dcce1 100644 --- a/llvm/test/tools/llvm-reduce/mir/preserve-reg-hints.mir +++ b/llvm/test/tools/llvm-reduce/mir/preserve-reg-hints.mir @@ -7,11 +7,11 @@ # Make sure that register hints are preserved in the cloned function. # RESULT: registers: -# RESULT-NEXT: - { id: 0, class: vgpr_32, preferred-register: '$vgpr0' } -# RESULT-NEXT: - { id: 1, class: vgpr_32, preferred-register: '' } -# RESULT-NEXT: - { id: 2, class: vgpr_32, preferred-register: '%1' } -# RESULT-NEXT: - { id: 3, class: vgpr_32, preferred-register: '%4' } -# RESULT-NEXT: - { id: 4, class: vgpr_32, preferred-register: '%3' } +# RESULT-NEXT: - { id: 0, class: vgpr_32, preferred-register: '$vgpr0', flags: [ ] } +# RESULT-NEXT: - { id: 1, class: vgpr_32, preferred-register: '', flags: [ ] } +# RESULT-NEXT: - { id: 2, class: vgpr_32, preferred-register: '%1', flags: [ ] } +# RESULT-NEXT: - { id: 3, class: vgpr_32, preferred-register: '%4', flags: [ ] } +# RESULT-NEXT: - { id: 4, class: vgpr_32, preferred-register: '%3', flags: [ ] } --- name: register_hints tracksRegLiveness: true From cdd93e201b27b75de4a4c7d78eb65ac7a1d7ff5c Mon Sep 17 00:00:00 2001 From: Akshat Oke Date: Fri, 4 Oct 2024 05:38:22 +0000 Subject: [PATCH 3/9] clang-format --- llvm/include/llvm/CodeGen/MIRParser/MIParser.h | 2 +- llvm/lib/CodeGen/MIRParser/MIParser.cpp | 5 +++-- llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 10 +++++----- 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/llvm/include/llvm/CodeGen/MIRParser/MIParser.h b/llvm/include/llvm/CodeGen/MIRParser/MIParser.h index a1a48f2fb02a8..531eb04a24630 100644 --- a/llvm/include/llvm/CodeGen/MIRParser/MIParser.h +++ b/llvm/include/llvm/CodeGen/MIRParser/MIParser.h @@ -151,7 +151,7 @@ struct PerTargetMIParsingState { /// Return null if the name isn't a register bank. const RegisterBank *getRegBank(StringRef Name); - bool getVRegFlagValue(StringRef FlagName, uint8_t& FlagValue) const; + bool getVRegFlagValue(StringRef FlagName, uint8_t &FlagValue) const; PerTargetMIParsingState(const TargetSubtargetInfo &STI) : Subtarget(STI) { diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp index f27fea1f748d9..92d23eeedb595 100644 --- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp @@ -127,11 +127,12 @@ bool PerTargetMIParsingState::getRegisterByName(StringRef RegName, return false; } -bool PerTargetMIParsingState::getVRegFlagValue(StringRef FlagName, uint8_t& FlagValue) const { +bool PerTargetMIParsingState::getVRegFlagValue(StringRef FlagName, + uint8_t &FlagValue) const { const auto *TRI = Subtarget.getRegisterInfo(); assert(TRI && "Expected target register info"); auto [HasVReg, FV] = TRI->getVRegFlagValue(FlagName); - if(!HasVReg) + if (!HasVReg) return true; FlagValue = FV; return false; diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp index 1f995c962a489..0c8a3eb6c2d83 100644 --- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp @@ -697,13 +697,13 @@ bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS, return error(Error, VReg.PreferredRegister.SourceRange); } - for(const auto &FlagStringValue: VReg.RegisterFlags) { + for (const auto &FlagStringValue : VReg.RegisterFlags) { uint8_t FlagValue; - if(Target->getVRegFlagValue(FlagStringValue.Value, FlagValue)) + if (Target->getVRegFlagValue(FlagStringValue.Value, FlagValue)) return error(FlagStringValue.SourceRange.Start, - Twine("use of undefined register flag '") + - FlagStringValue.Value + "'"); - Info.Flags.push_back(FlagValue); + Twine("use of undefined register flag '") + + FlagStringValue.Value + "'"); + Info.Flags.push_back(FlagValue); } } From 190a4b2d9fb36de14d0331e470a9d57d6646d718 Mon Sep 17 00:00:00 2001 From: Akshat Oke Date: Fri, 4 Oct 2024 06:06:48 +0000 Subject: [PATCH 4/9] SmallString, std::optional, enum : uint8_t --- llvm/include/llvm/CodeGen/MIRParser/MIParser.h | 4 ++-- llvm/include/llvm/CodeGen/TargetRegisterInfo.h | 6 +++--- llvm/lib/CodeGen/MIRParser/MIParser.cpp | 7 +++---- llvm/lib/CodeGen/MIRPrinter.cpp | 4 ++-- 4 files changed, 10 insertions(+), 11 deletions(-) diff --git a/llvm/include/llvm/CodeGen/MIRParser/MIParser.h b/llvm/include/llvm/CodeGen/MIRParser/MIParser.h index 531eb04a24630..21471705fc43f 100644 --- a/llvm/include/llvm/CodeGen/MIRParser/MIParser.h +++ b/llvm/include/llvm/CodeGen/MIRParser/MIParser.h @@ -37,7 +37,7 @@ class TargetRegisterClass; class TargetSubtargetInfo; struct VRegInfo { - enum uint8_t { + enum : uint8_t { UNKNOWN, NORMAL, GENERIC, REGBANK } Kind = UNKNOWN; bool Explicit = false; ///< VReg was explicitly specified in the .mir file. @@ -47,7 +47,7 @@ struct VRegInfo { } D; Register VReg; Register PreferredReg; - std::vector<::uint8_t> Flags; + std::vector Flags; }; using Name2RegClassMap = StringMap; diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h index 6ec38ebb4f886..3a7a2dc6ce4fe 100644 --- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h +++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h @@ -1214,11 +1214,11 @@ class TargetRegisterInfo : public MCRegisterInfo { return false; } - virtual std::pair getVRegFlagValue(StringRef Name) const { - return {false, 0}; + virtual std::optional getVRegFlagValue(StringRef Name) const { + return {}; } - virtual SmallVector + virtual SmallVector> getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const { return {}; } diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp index 92d23eeedb595..88ae99079d842 100644 --- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp @@ -130,11 +130,10 @@ bool PerTargetMIParsingState::getRegisterByName(StringRef RegName, bool PerTargetMIParsingState::getVRegFlagValue(StringRef FlagName, uint8_t &FlagValue) const { const auto *TRI = Subtarget.getRegisterInfo(); - assert(TRI && "Expected target register info"); - auto [HasVReg, FV] = TRI->getVRegFlagValue(FlagName); - if (!HasVReg) + auto FV = TRI->getVRegFlagValue(FlagName); + if (!FV.has_value()) return true; - FlagValue = FV; + FlagValue = FV.value(); return false; } diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp index 8791e41ad613c..5a17db44abbd5 100644 --- a/llvm/lib/CodeGen/MIRPrinter.cpp +++ b/llvm/lib/CodeGen/MIRPrinter.cpp @@ -321,9 +321,9 @@ static void printRegFlags(Register Reg, std::vector &RegisterFlags, const MachineFunction &MF, const TargetRegisterInfo *TRI) { - SmallVector FlagValues = TRI->getVRegFlagsOfReg(Reg, MF); + auto FlagValues = TRI->getVRegFlagsOfReg(Reg, MF); for (auto &Flag : FlagValues) { - RegisterFlags.push_back(yaml::FlowStringValue(Flag)); + RegisterFlags.push_back(yaml::FlowStringValue(Flag.str().str())); } } From 558af426479be60767dbc23a2e0e5a55e93a8a24 Mon Sep 17 00:00:00 2001 From: Akshat Oke Date: Fri, 4 Oct 2024 06:08:04 +0000 Subject: [PATCH 5/9] Add failing test --- .../CodeGen/MIR/Generic/register-flag-error.mir | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 llvm/test/CodeGen/MIR/Generic/register-flag-error.mir diff --git a/llvm/test/CodeGen/MIR/Generic/register-flag-error.mir b/llvm/test/CodeGen/MIR/Generic/register-flag-error.mir new file mode 100644 index 0000000000000..a35b7502ad4ac --- /dev/null +++ b/llvm/test/CodeGen/MIR/Generic/register-flag-error.mir @@ -0,0 +1,13 @@ +# RUN: not llc -run-pass=none -o - %s 2>&1 | FileCheck %s --check-prefix=ERR + +--- +name: flags +registers: + - { id: 0, class: _, flags: [ 'VFLAG_ERR' ] } +body: | + bb.0: + liveins: $w0 + %0 = G_ADD $w0, $w0 +... +# ERR: use of undefined register flag +# ERR: VFLAG_ERR \ No newline at end of file From dabe1ecd6fc5744d531dc7baa67fdef6eed1fcf8 Mon Sep 17 00:00:00 2001 From: Akshat Oke Date: Tue, 8 Oct 2024 06:24:39 +0000 Subject: [PATCH 6/9] AS --- llvm/lib/CodeGen/MIRParser/MIParser.cpp | 6 +++--- llvm/test/CodeGen/MIR/Generic/register-flag-error.mir | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp index 88ae99079d842..7aaa0f409d5ef 100644 --- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp @@ -130,10 +130,10 @@ bool PerTargetMIParsingState::getRegisterByName(StringRef RegName, bool PerTargetMIParsingState::getVRegFlagValue(StringRef FlagName, uint8_t &FlagValue) const { const auto *TRI = Subtarget.getRegisterInfo(); - auto FV = TRI->getVRegFlagValue(FlagName); - if (!FV.has_value()) + std::optional FV = TRI->getVRegFlagValue(FlagName); + if (!FV) return true; - FlagValue = FV.value(); + FlagValue = *FV; return false; } diff --git a/llvm/test/CodeGen/MIR/Generic/register-flag-error.mir b/llvm/test/CodeGen/MIR/Generic/register-flag-error.mir index a35b7502ad4ac..efbcf23af071e 100644 --- a/llvm/test/CodeGen/MIR/Generic/register-flag-error.mir +++ b/llvm/test/CodeGen/MIR/Generic/register-flag-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -run-pass=none -o - %s 2>&1 | FileCheck %s --check-prefix=ERR +# RUN: not llc -run-pass=none -filetype=null %s 2>&1 | FileCheck %s --check-prefix=ERR --- name: flags @@ -10,4 +10,4 @@ body: | %0 = G_ADD $w0, $w0 ... # ERR: use of undefined register flag -# ERR: VFLAG_ERR \ No newline at end of file +# ERR: VFLAG_ERR From 902f04eb7b6d191ccd6825121d27ebfd36dce17c Mon Sep 17 00:00:00 2001 From: Akshat Oke Date: Wed, 9 Oct 2024 04:59:33 +0000 Subject: [PATCH 7/9] Moving the noteNewVirtualRegister change to a new commit --- llvm/lib/CodeGen/MIRParser/MIParser.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp index 7aaa0f409d5ef..f1d3ce9a56340 100644 --- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp @@ -1786,7 +1786,6 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest, MRI.setRegClassOrRegBank(Reg, static_cast(nullptr)); MRI.setType(Reg, Ty); - MRI.noteNewVirtualRegister(Reg); } } } else if (consumeIfPresent(MIToken::lparen)) { From d3dc95f95cd234d9b34374e7271c9fe27c7aaecb Mon Sep 17 00:00:00 2001 From: Akshat Oke Date: Wed, 9 Oct 2024 05:52:59 +0000 Subject: [PATCH 8/9] StringLiteral --- llvm/include/llvm/CodeGen/TargetRegisterInfo.h | 2 +- llvm/lib/CodeGen/MIRPrinter.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h index 3a7a2dc6ce4fe..292fa3c94969b 100644 --- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h +++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h @@ -1218,7 +1218,7 @@ class TargetRegisterInfo : public MCRegisterInfo { return {}; } - virtual SmallVector> + virtual SmallVector getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const { return {}; } diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp index 5a17db44abbd5..a015cd3c2a55f 100644 --- a/llvm/lib/CodeGen/MIRPrinter.cpp +++ b/llvm/lib/CodeGen/MIRPrinter.cpp @@ -323,7 +323,7 @@ static void printRegFlags(Register Reg, const TargetRegisterInfo *TRI) { auto FlagValues = TRI->getVRegFlagsOfReg(Reg, MF); for (auto &Flag : FlagValues) { - RegisterFlags.push_back(yaml::FlowStringValue(Flag.str().str())); + RegisterFlags.push_back(yaml::FlowStringValue(Flag.str())); } } From 5e1c572a4afcfa3e19b66b6d96979d0b62d31c54 Mon Sep 17 00:00:00 2001 From: Akshat Oke Date: Wed, 9 Oct 2024 06:05:22 +0000 Subject: [PATCH 9/9] clang-format --- llvm/include/llvm/CodeGen/MIRParser/MIParser.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/llvm/include/llvm/CodeGen/MIRParser/MIParser.h b/llvm/include/llvm/CodeGen/MIRParser/MIParser.h index 21471705fc43f..4d93213de5e07 100644 --- a/llvm/include/llvm/CodeGen/MIRParser/MIParser.h +++ b/llvm/include/llvm/CodeGen/MIRParser/MIParser.h @@ -37,9 +37,7 @@ class TargetRegisterClass; class TargetSubtargetInfo; struct VRegInfo { - enum : uint8_t { - UNKNOWN, NORMAL, GENERIC, REGBANK - } Kind = UNKNOWN; + enum : uint8_t { UNKNOWN, NORMAL, GENERIC, REGBANK } Kind = UNKNOWN; bool Explicit = false; ///< VReg was explicitly specified in the .mir file. union { const TargetRegisterClass *RC;