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[AMDGPU] Make more use of getWaveMaskRegClass. NFC. #108186

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Merged
merged 1 commit into from
Sep 11, 2024
Merged

[AMDGPU] Make more use of getWaveMaskRegClass. NFC. #108186

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4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1116,8 +1116,8 @@ void SIFixSGPRCopies::fixSCCCopies(MachineFunction &MF) {
Register SrcReg = MI.getOperand(1).getReg();
Register DstReg = MI.getOperand(0).getReg();
if (SrcReg == AMDGPU::SCC) {
Register SCCCopy = MRI->createVirtualRegister(
TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID));
Register SCCCopy =
MRI->createVirtualRegister(TRI->getWaveMaskRegClass());
I = BuildMI(*MI.getParent(), std::next(MachineBasicBlock::iterator(MI)),
MI.getDebugLoc(),
TII->get(IsWave32 ? AMDGPU::S_CSELECT_B32
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Expand Up @@ -4562,7 +4562,7 @@ loadM0FromVGPR(const SIInstrInfo *TII, MachineBasicBlock &MBB, MachineInstr &MI,
const DebugLoc &DL = MI.getDebugLoc();
MachineBasicBlock::iterator I(&MI);

const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
const auto *BoolXExecRC = TRI->getWaveMaskRegClass();
Register DstReg = MI.getOperand(0).getReg();
Register SaveExec = MRI.createVirtualRegister(BoolXExecRC);
Register TmpExec = MRI.createVirtualRegister(BoolXExecRC);
Expand Down Expand Up @@ -5064,7 +5064,7 @@ MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(
return BB;
}

const auto *CarryRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
const auto *CarryRC = TRI->getWaveMaskRegClass();

Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
Expand Down Expand Up @@ -5296,7 +5296,7 @@ MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(

Register DstLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
Register DstHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
const auto *CondRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
const auto *CondRC = TRI->getWaveMaskRegClass();
Register SrcCondCopy = MRI.createVirtualRegister(CondRC);

const TargetRegisterClass *Src0RC = Src0.isReg()
Expand Down
14 changes: 6 additions & 8 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Expand Up @@ -1231,8 +1231,7 @@ void SIInstrInfo::insertVectorSelect(MachineBasicBlock &MBB,
Register TrueReg,
Register FalseReg) const {
MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
const TargetRegisterClass *BoolXExecRC =
RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
const TargetRegisterClass *BoolXExecRC = RI.getWaveMaskRegClass();
assert(MRI.getRegClass(DstReg) == &AMDGPU::VGPR_32RegClass &&
"Not a VGPR32 reg");

Expand Down Expand Up @@ -6417,7 +6416,7 @@ static void emitLoadScalarOpsFromVGPRLoop(
ST.isWave32() ? AMDGPU::S_XOR_B32_term : AMDGPU::S_XOR_B64_term;
unsigned AndOpc =
ST.isWave32() ? AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64;
const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
const auto *BoolXExecRC = TRI->getWaveMaskRegClass();

MachineBasicBlock::iterator I = LoopBB.begin();

Expand Down Expand Up @@ -6565,7 +6564,7 @@ loadMBUFScalarOperandsFromVGPR(const SIInstrInfo &TII, MachineInstr &MI,
const DebugLoc &DL = MI.getDebugLoc();
unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
unsigned MovExecOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
const auto *BoolXExecRC = TRI->getWaveMaskRegClass();

// Save SCC. Waterfall Loop may overwrite SCC.
Register SaveSCCReg;
Expand Down Expand Up @@ -6958,7 +6957,7 @@ SIInstrInfo::legalizeOperands(MachineInstr &MI,
Register NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
Register NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);

const auto *BoolXExecRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
const auto *BoolXExecRC = RI.getWaveMaskRegClass();
Register CondReg0 = MRI.createVirtualRegister(BoolXExecRC);
Register CondReg1 = MRI.createVirtualRegister(BoolXExecRC);

Expand Down Expand Up @@ -7336,7 +7335,7 @@ void SIInstrInfo::moveToVALUImpl(SIInstrWorklist &Worklist,
unsigned Opc = (Inst.getOpcode() == AMDGPU::S_ADD_CO_PSEUDO)
? AMDGPU::V_ADDC_U32_e64
: AMDGPU::V_SUBB_U32_e64;
const auto *CarryRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
const auto *CarryRC = RI.getWaveMaskRegClass();

Register CarryInReg = Inst.getOperand(4).getReg();
if (!MRI.constrainRegClass(CarryInReg, CarryRC)) {
Expand Down Expand Up @@ -7711,8 +7710,7 @@ void SIInstrInfo::lowerSelect(SIInstrWorklist &Worklist, MachineInstr &Inst,

Register NewCondReg = CondReg;
if (IsSCC) {
const TargetRegisterClass *TC =
RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
const TargetRegisterClass *TC = RI.getWaveMaskRegClass();
NewCondReg = MRI.createVirtualRegister(TC);

// Now look for the closest SCC def if it is a copy
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2014,7 +2014,7 @@ Register SILoadStoreOptimizer::computeBase(MachineInstr &MI,
MachineOperand OffsetHi =
createRegOrImm(static_cast<int32_t>(Addr.Offset >> 32), MI);

const auto *CarryRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
const auto *CarryRC = TRI->getWaveMaskRegClass();
Register CarryReg = MRI->createVirtualRegister(CarryRC);
Register DeadCarryReg = MRI->createVirtualRegister(CarryRC);

Expand Down
6 changes: 2 additions & 4 deletions llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
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Expand Up @@ -3428,8 +3428,7 @@ SIRegisterInfo::getRegClassForSizeOnBank(unsigned Size,
std::max(ST.useRealTrue16Insts() ? 16u : 32u, Size));
case AMDGPU::VCCRegBankID:
assert(Size == 1);
return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass
: &AMDGPU::SReg_64_XEXECRegClass;
return getWaveMaskRegClass();
case AMDGPU::SGPRRegBankID:
return getSGPRClassForBitWidth(std::max(32u, Size));
case AMDGPU::AGPRRegBankID:
Expand Down Expand Up @@ -3472,8 +3471,7 @@ SIRegisterInfo::getRegClass(unsigned RCID) const {
case AMDGPU::SReg_1RegClassID:
return getBoolRC();
case AMDGPU::SReg_1_XEXECRegClassID:
return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass
: &AMDGPU::SReg_64_XEXECRegClass;
return getWaveMaskRegClass();
case -1:
return nullptr;
default:
Expand Down