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Description
| Bugzilla Link | 45705 |
| Resolution | FIXED |
| Resolved on | May 19, 2020 12:27 |
| Version | 10.0 |
| OS | All |
| Blocks | #44654 |
| CC | @TNorthover,@tstellar |
| Fixed by commit(s) | 8807139 f3164f7 |
Extended Description
Please merge https://reviews.llvm.org/rG8807139026b64ac40163bb255dad38a1d8054f08 into 10.0.1. This fixes bug 45677, a fatal backend error when targeting armv5:
Author: David Green
Date: 2020-04-27T10:13:29+01:00
New Revision: 8807139
URL: 8807139
DIFF: https://github.com/llvm/llvm-project/commit/8807139026b64ac40163bb255dad38a1d8054f08.diff
LOG: [ARM] Only produce qadd8b under hasV6Ops
When compiling for a arm5te cpu from clang, the +dsp attribute is set.
This meant we could try and generate qadd8 instructions where we would
end up having no pattern. I've changed the condition here to be hasV6Ops
&& hasDSP, which is what other parts of ARMISelLowering seem to use for
similar instructions.
Fixed #45022 .
Differential Revision: https://reviews.llvm.org/D78877