fixup! [RISCV] RISCV vector calling convention (2/2)

Author: 4vtomat

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -20531,7 +20531,7 @@ unsigned RISCVTargetLowering::getMinimumJumpTableEntries() const {
   return Subtarget.getMinimumJumpTableEntries();
 }
 
-void RVVArgDispatcher::constructHelper(Type *Ty) {
+void RVVArgDispatcher::constructArgInfos(Type *Ty) {
   const DataLayout &DL = MF->getDataLayout();
   const Function &F = MF->getFunction();
   LLVMContext &Context = F.getContext();
@@ -20564,16 +20564,14 @@ void RVVArgDispatcher::constructHelper(Type *Ty) {
         RegisterVT = TLI->getContainerForFixedLengthVector(RegisterVT);
 
       RVVArgInfo Info{1, RegisterVT, false};
-
-      while (NumRegs--)
-        RVVArgInfos.push_back(Info);
+      RVVArgInfos.insert(RVVArgInfos.end(), NumRegs, Info);
     }
   }
 }
 
-void RVVArgDispatcher::construct(std::vector<Type *> &TypeList) {
+void RVVArgDispatcher::construct(const std::vector<Type *> &TypeList) {
   for (Type *Ty : TypeList)
-    constructHelper(Ty);
+    constructArgInfos(Ty);
 
   for (auto &Info : RVVArgInfos)
     if (Info.NF == 1 && Info.VT.getVectorElementType() == MVT::i1) {
@@ -20608,28 +20606,27 @@ void RVVArgDispatcher::allocatePhysReg(unsigned NF, unsigned LMul,
     if (StartReg)
       AllocatedPhysRegs.push_back(VRArrays[(StartReg - 8) / LMul + i]);
     else
-      AllocatedPhysRegs.push_back(0);
+      AllocatedPhysRegs.push_back(MCPhysReg());
 }
 
-// This function determines if each RVV argument is passed by register.
+/// This function determines if each RVV argument is passed by register, if the
+/// argument can be assigned to a VR, then give it a specific register.
+/// Otherwise, assign the argument to 0 which is a invalid MCPhysReg.
 void RVVArgDispatcher::compute() {
-  unsigned ToBeAssigned = RVVArgInfos.size();
-  uint64_t AssignedMap = 0;
-  auto tryAllocate = [&](const RVVArgInfo &ArgInfo) {
+  uint32_t AssignedMap = 0;
+  auto allocate = [&](const RVVArgInfo &ArgInfo) {
     // Allocate first vector mask argument to V0.
     if (ArgInfo.FirstVMask) {
       AllocatedPhysRegs.push_back(RISCV::V0);
       return;
     }
 
-    unsigned RegsNeeded =
-        std::max((unsigned)ArgInfo.VT.getSizeInBits().getKnownMinValue() /
-                     RISCV::RVVBitsPerBlock,
-                 (unsigned)1);
+    unsigned RegsNeeded = divideCeil(
+        ArgInfo.VT.getSizeInBits().getKnownMinValue(), RISCV::RVVBitsPerBlock);
     unsigned TotalRegsNeeded = ArgInfo.NF * RegsNeeded;
     for (unsigned StartReg = 0; StartReg + TotalRegsNeeded <= NumArgVRs;
          StartReg += RegsNeeded) {
-      unsigned Map = ((1 << TotalRegsNeeded) - 1) << StartReg;
+      uint32_t Map = ((1 << TotalRegsNeeded) - 1) << StartReg;
       if ((AssignedMap & Map) == 0) {
         allocatePhysReg(ArgInfo.NF, RegsNeeded, StartReg + 8);
         AssignedMap |= Map;
@@ -20638,11 +20635,10 @@ void RVVArgDispatcher::compute() {
     }
 
     allocatePhysReg(ArgInfo.NF, RegsNeeded, 0);
-    return;
   };
 
-  for (unsigned i = 0; i < ToBeAssigned; ++i)
-    tryAllocate(RVVArgInfos[i]);
+  for (unsigned i = 0; i < RVVArgInfos.size(); ++i)
+    allocate(RVVArgInfos[i]);
 }
 
 MCPhysReg RVVArgDispatcher::getNextPhysReg() {

llvm/lib/Target/RISCV/RISCVISelLowering.h

@@ -1010,6 +1010,21 @@ class RISCVTargetLowering : public TargetLowering {
   unsigned getMinimumJumpTableEntries() const override;
 };
 
+/// As per the spec, the rules for passing vector arguments are as follows:
+///
+/// 1. For the first vector mask argument, use v0 to pass it.
+/// 2. For vector data arguments or rest vector mask arguments, starting from
+/// the v8 register, if a vector register group between v8-v23 that has not been
+/// allocated can be found and the first register number is a multiple of LMUL,
+/// then allocate this vector register group to the argument and mark these
+/// registers as allocated. Otherwise, pass it by reference and are replaced in
+/// the argument list with the address.
+/// 3. For tuple vector data arguments, starting from the v8 register, if
+/// NFIELDS consecutive vector register groups between v8-v23 that have not been
+/// allocated can be found and the first register number is a multiple of LMUL,
+/// then allocate these vector register groups to the argument and mark these
+/// registers as allocated. Otherwise, pass it by reference and are replaced in
+/// the argument list with the address.
 class RVVArgDispatcher {
 public:
   static constexpr unsigned NumArgVRs = 16;
@@ -1043,13 +1058,11 @@ class RVVArgDispatcher {
 
   const MachineFunction *MF = nullptr;
   const RISCVTargetLowering *TLI = nullptr;
-  TargetLowering::CallLoweringInfo *CLI = nullptr;
-  CallLowering::CallLoweringInfo *GISelCLI = nullptr;
 
   unsigned CurIdx = 0;
 
-  void construct(std::vector<Type *> &TypeList);
-  void constructHelper(Type *Ty);
+  void construct(const std::vector<Type *> &TypeList);
+  void constructArgInfos(Type *Ty);
   void compute();
   void allocatePhysReg(unsigned NF = 1, unsigned LMul = 1,
                        unsigned StartReg = 0);