Removed redundant loops, updated comments

Author: Tony Varghese

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

@@ -9679,13 +9679,6 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
   BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
   assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
 
-  // Recognize build vector patterns to emit VSX vector instructions
-  // instead of loading value from memory.
-  if (Subtarget.isISA3_1() && Subtarget.hasVSX()) {
-    if (SDValue VecPat = combineBVLoadsSpecialValue(Op, DAG))
-      return VecPat;
-  }
-
   if (Subtarget.hasP10Vector()) {
     APInt BitMask(32, 0);
     // If the value of the vector is all zeros or all ones,
@@ -9705,6 +9698,10 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
       }
       return SDV;
     }
+    // Recognize build vector patterns to emit VSX vector instructions
+    // instead of loading value from memory.
+    if (SDValue VecPat = combineBVLoadsSpecialValue(Op, DAG))
+      return VecPat;
   }
   // Check if this is a splat of a constant value.
   APInt APSplatBits, APSplatUndef;
@@ -15679,31 +15676,35 @@ using LXVKQPattern = std::tuple<uint32_t, uint8_t>;
 
 static std::optional<LXVKQPattern> getPatternInfo(const APInt &FullVal) {
 
-  static const auto BaseLXVKQPatterns = []() {
-    // LXVKQ instruction loads the Quadword value:
-    // 0x8000_0000_0000_0000_0000_0000_0000_0000 when imm = 0b10000
-    return std::array<std::pair<APInt, uint32_t>, 1>{
-        {{APInt(128, 0x8000000000000000ULL) << 64, 16}}};
-  }();
+  // LXVKQ instruction loads the Quadword value:
+  // 0x8000_0000_0000_0000_0000_0000_0000_0000 when imm = 0b10000
+  static const APInt BasePattern = APInt(128, 0x8000000000000000ULL) << 64;
+  static const uint32_t Uim = 16;
 
   // Check for direct LXVKQ match (no shift needed)
-  for (const auto &[BasePattern, Uim] : BaseLXVKQPatterns) {
-    if (FullVal == BasePattern)
-      return std::make_tuple(Uim, uint8_t{0});
-  }
+  if (FullVal == BasePattern)
+    return std::make_tuple(Uim, uint8_t{0});
 
-  // Check if FullValue can be generated by (right) shifting a base pattern
-  for (const auto &[BasePattern, Uim] : BaseLXVKQPatterns) {
-    if (BasePattern.lshr(127) == FullVal)
-      return std::make_tuple(Uim, uint8_t{127});
-  }
+  // Check if FullValue is 1 (the result of the base pattern >> 127)
+  if (FullVal == APInt(128, 1))
+    return std::make_tuple(Uim, uint8_t{127});
 
   return std::nullopt;
 }
 
-/// Combine vector loads to a single load by recognising patterns in the Build
-/// Vector. LXVKQ instruction load VSX vector with a special quadword value
-/// based on an immediate value.
+/// Combine vector loads to a single load (using lxvkq) or splat with shift of a
+/// constant (xxspltib + vsrq) by recognising patterns in the Build Vector.
+/// LXVKQ instruction load VSX vector with a special quadword value based on an
+/// immediate value. if UIM=0b10000 then LXVKQ loads VSR[32×TX+T] with value
+/// 0x8000_0000_0000_0000_0000_0000_0000_0000.
+/// This can be used to inline the build vector constants that have the
+/// following patterns:
+///
+/// 0x8000_0000_0000_0000_0000_0000_0000_0000 (MSB set pattern)
+/// 0x0000_0000_0000_0000_0000_0000_0000_0001 (LSB set pattern)
+/// MSB pattern can directly loaded using LXVKQ while LSB is loaded using a
+/// combination of splatting and right shift instructions.
+
 SDValue PPCTargetLowering::combineBVLoadsSpecialValue(SDValue Op,
                                                       SelectionDAG &DAG) const {
 
@@ -15775,8 +15776,8 @@ SDValue PPCTargetLowering::combineBVLoadsSpecialValue(SDValue Op,
     }
 
     // The right shifted pattern can be constructed using a combination of
-    // XXSPLITIB and VSRQ instruction. VSRQ uses the shift amount from the lower
-    // 7 bits of byte 15. This can be specified using XXSPLITIB with immediate
+    // XXSPLTIB and VSRQ instruction. VSRQ uses the shift amount from the lower
+    // 7 bits of byte 15. This can be specified using XXSPLTIB with immediate
     // value 255.
     SDValue ShiftAmountVec =
         SDValue(DAG.getMachineNode(PPC::XXSPLTIB, Dl, MVT::v4i32,