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Fix index range for write.lane.zt
1 parent 115ef77 commit fad06af

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4 files changed

+15
-43
lines changed

4 files changed

+15
-43
lines changed

‎clang/include/clang/Basic/arm_sme.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -820,7 +820,7 @@ defm SVREADZ_VG4 : ZAReadzArray<"4">;
820820

821821
let SMETargetGuard = "sme2,sme-lutv2" in {
822822
def SVLUTI4_ZT_X4 : SInst<"svluti4_zt_{d}_x4", "4i2.u", "cUc", MergeNone, "aarch64_sme_luti4_zt_x4", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>]>;
823-
def SVWRITE_LANE_ZT : SInst<"svwrite_lane_zt[_{d}]", "vidi", "cUcsUsiUilUlfhdb", MergeNone, "aarch64_sme_write_lane_zt", [IsStreaming, IsInOutZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>;
823+
def SVWRITE_LANE_ZT : SInst<"svwrite_lane_zt[_{d}]", "vidi", "cUcsUsiUilUlfhdb", MergeNone, "aarch64_sme_write_lane_zt", [IsStreaming, IsInOutZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck1_3>]>;
824824
def SVWRITE_ZT : SInst<"svwrite_zt[_{d}]", "vid", "cUcsUsiUilUlfhdb", MergeNone, "aarch64_sme_write_zt", [IsStreaming, IsOutZT0], [ImmCheck<0, ImmCheck0_0>]>;
825825
}
826826
} // let SVETargetGuard = InvalidMode

‎clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_write_lane_zt.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -114,17 +114,17 @@ void test_write_lane_zt_s32_3(svint32_t v) __arm_streaming __arm_inout("zt0") {
114114
// CHECK-LABEL: define dso_local void @test_write_lane_zt_u64_0(
115115
// CHECK-SAME: <vscale x 2 x i64> [[V:%.*]]) local_unnamed_addr #[[ATTR0]] {
116116
// CHECK-NEXT: [[ENTRY:.*:]]
117-
// CHECK-NEXT: tail call void @llvm.aarch64.sme.write.lane.zt.nxv2i64(i32 0, <vscale x 2 x i64> [[V]], i32 0)
117+
// CHECK-NEXT: tail call void @llvm.aarch64.sme.write.lane.zt.nxv2i64(i32 0, <vscale x 2 x i64> [[V]], i32 1)
118118
// CHECK-NEXT: ret void
119119
//
120120
// CHECK-CXX-LABEL: define dso_local void @_Z24test_write_lane_zt_u64_0u12__SVUint64_t(
121121
// CHECK-CXX-SAME: <vscale x 2 x i64> [[V:%.*]]) local_unnamed_addr #[[ATTR0]] {
122122
// CHECK-CXX-NEXT: [[ENTRY:.*:]]
123-
// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.write.lane.zt.nxv2i64(i32 0, <vscale x 2 x i64> [[V]], i32 0)
123+
// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.write.lane.zt.nxv2i64(i32 0, <vscale x 2 x i64> [[V]], i32 1)
124124
// CHECK-CXX-NEXT: ret void
125125
//
126126
void test_write_lane_zt_u64_0(svuint64_t v) __arm_streaming __arm_inout("zt0") {
127-
SVE_ACLE_FUNC(svwrite_lane_zt, _u64)(0, v, 0);
127+
SVE_ACLE_FUNC(svwrite_lane_zt, _u64)(0, v, 1);
128128
}
129129

130130
// CHECK-LABEL: define dso_local void @test_write_lane_zt_s64_1(
@@ -178,17 +178,17 @@ void test_write_lane_zt_bf16_3(svbfloat16_t v) __arm_streaming __arm_inout("zt0"
178178
// CHECK-LABEL: define dso_local void @test_write_lane_zt_f32_0(
179179
// CHECK-SAME: <vscale x 4 x float> [[V:%.*]]) local_unnamed_addr #[[ATTR0]] {
180180
// CHECK-NEXT: [[ENTRY:.*:]]
181-
// CHECK-NEXT: tail call void @llvm.aarch64.sme.write.lane.zt.nxv4f32(i32 0, <vscale x 4 x float> [[V]], i32 0)
181+
// CHECK-NEXT: tail call void @llvm.aarch64.sme.write.lane.zt.nxv4f32(i32 0, <vscale x 4 x float> [[V]], i32 2)
182182
// CHECK-NEXT: ret void
183183
//
184184
// CHECK-CXX-LABEL: define dso_local void @_Z24test_write_lane_zt_f32_0u13__SVFloat32_t(
185185
// CHECK-CXX-SAME: <vscale x 4 x float> [[V:%.*]]) local_unnamed_addr #[[ATTR0]] {
186186
// CHECK-CXX-NEXT: [[ENTRY:.*:]]
187-
// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.write.lane.zt.nxv4f32(i32 0, <vscale x 4 x float> [[V]], i32 0)
187+
// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.write.lane.zt.nxv4f32(i32 0, <vscale x 4 x float> [[V]], i32 2)
188188
// CHECK-CXX-NEXT: ret void
189189
//
190190
void test_write_lane_zt_f32_0(svfloat32_t v) __arm_streaming __arm_inout("zt0") {
191-
SVE_ACLE_FUNC(svwrite_lane_zt, _f32)(0, v, 0);
191+
SVE_ACLE_FUNC(svwrite_lane_zt, _f32)(0, v, 2);
192192
}
193193

194194
// CHECK-LABEL: define dso_local void @test_write_lane_zt_f64_1(

‎clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_imm.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -361,5 +361,6 @@ void test_read_zt() __arm_streaming __arm_inout("zt0") {
361361
svwrite_lane_zt(1, svundef_s8(), 1); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
362362
svwrite_zt(1, svundef_s8()); // expected-error {{argument value 1 is outside the valid range [0, 0]}}
363363
// Check index
364-
svwrite_lane_zt(0, svundef_s8(), 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
364+
svwrite_lane_zt(0, svundef_s8(), 0); // expected-error {{argument value 4 is outside the valid range [1, 3]}}
365+
svwrite_lane_zt(0, svundef_s8(), 4); // expected-error {{argument value 4 is outside the valid range [1, 3]}}
365366
}

‎llvm/lib/Target/AArch64/SMEInstrFormats.td‎

Lines changed: 6 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -3292,41 +3292,12 @@ multiclass sme2_movt_zt_to_zt<string mnemonic, bits<7> opc, SDPatternOperator in
32923292
def : InstAlias<mnemonic # "\t$ZTt, $Zt",
32933293
(!cast<Instruction>(NAME) ZTR:$ZTt, 0, ZPRAny:$Zt), 1>;
32943294

3295-
def : Pat<(intrinsic_lane (imm_to_zt untyped:$zt), nxv16i8:$zn, sme_elm_idx0_3:$imm),
3296-
(!cast<Instruction>(NAME # _PSEUDO) $zt, sme_elm_idx0_3:$imm, $zn)>;
3297-
def : Pat<(intrinsic_lane (imm_to_zt untyped:$zt), nxv8i16:$zn, sme_elm_idx0_3:$imm),
3298-
(!cast<Instruction>(NAME # _PSEUDO) $zt, sme_elm_idx0_3:$imm, $zn)>;
3299-
def : Pat<(intrinsic_lane (imm_to_zt untyped:$zt), nxv4i32:$zn, sme_elm_idx0_3:$imm),
3300-
(!cast<Instruction>(NAME # _PSEUDO) $zt, sme_elm_idx0_3:$imm, $zn)>;
3301-
def : Pat<(intrinsic_lane (imm_to_zt untyped:$zt), nxv2i64:$zn, sme_elm_idx0_3:$imm),
3302-
(!cast<Instruction>(NAME # _PSEUDO) $zt, sme_elm_idx0_3:$imm, $zn)>;
3303-
def : Pat<(intrinsic_lane (imm_to_zt untyped:$zt), nxv8f16:$zn, sme_elm_idx0_3:$imm),
3304-
(!cast<Instruction>(NAME # _PSEUDO) $zt, sme_elm_idx0_3:$imm, $zn)>;
3305-
def : Pat<(intrinsic_lane (imm_to_zt untyped:$zt), nxv4f32:$zn, sme_elm_idx0_3:$imm),
3306-
(!cast<Instruction>(NAME # _PSEUDO) $zt, sme_elm_idx0_3:$imm, $zn)>;
3307-
def : Pat<(intrinsic_lane (imm_to_zt untyped:$zt), nxv2f64:$zn, sme_elm_idx0_3:$imm),
3308-
(!cast<Instruction>(NAME # _PSEUDO) $zt, sme_elm_idx0_3:$imm, $zn)>;
3309-
def : Pat<(intrinsic_lane (imm_to_zt untyped:$zt), nxv8bf16:$zn, sme_elm_idx0_3:$imm),
3310-
(!cast<Instruction>(NAME # _PSEUDO) $zt, sme_elm_idx0_3:$imm, $zn)>;
3311-
3312-
//Alias intrinsic
3313-
def : Pat<(intrinsic (imm_to_zt untyped:$zt), nxv16i8:$zn),
3314-
(!cast<Instruction>(NAME # _PSEUDO) $zt, 0, $zn)>;
3315-
def : Pat<(intrinsic (imm_to_zt untyped:$zt), nxv8i16:$zn),
3316-
(!cast<Instruction>(NAME # _PSEUDO) $zt, 0, $zn)>;
3317-
def : Pat<(intrinsic (imm_to_zt untyped:$zt), nxv4i32:$zn),
3318-
(!cast<Instruction>(NAME # _PSEUDO) $zt, 0, $zn)>;
3319-
def : Pat<(intrinsic (imm_to_zt untyped:$zt), nxv2i64:$zn),
3320-
(!cast<Instruction>(NAME # _PSEUDO) $zt, 0, $zn)>;
3321-
def : Pat<(intrinsic (imm_to_zt untyped:$zt), nxv8f16:$zn),
3322-
(!cast<Instruction>(NAME # _PSEUDO) $zt, 0, $zn)>;
3323-
def : Pat<(intrinsic (imm_to_zt untyped:$zt), nxv4f32:$zn),
3324-
(!cast<Instruction>(NAME # _PSEUDO) $zt, 0, $zn)>;
3325-
def : Pat<(intrinsic (imm_to_zt untyped:$zt), nxv2f64:$zn),
3326-
(!cast<Instruction>(NAME # _PSEUDO) $zt, 0, $zn)>;
3327-
def : Pat<(intrinsic (imm_to_zt untyped:$zt), nxv8bf16:$zn),
3328-
(!cast<Instruction>(NAME # _PSEUDO) $zt, 0, $zn)>;
3329-
3295+
foreach vt = [nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv8f16, nxv4f32, nxv2f64, nxv8bf16] in {
3296+
def : Pat<(intrinsic_lane (imm_to_zt untyped:$zt), vt:$zn, sme_elm_idx0_3:$imm),
3297+
(!cast<Instruction>(NAME # _PSEUDO) $zt, $imm, $zn)>;
3298+
def : Pat<(intrinsic (imm_to_zt untyped:$zt), vt:$zn),
3299+
(!cast<Instruction>(NAME # _PSEUDO) $zt, 0, $zn)>;
3300+
}
33303301
}
33313302

33323303
//===----------------------------------------------------------------------===//

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