fixup! [AArch64][llvm] Armv9.7-A: Add support for SVE2p3 shift operations

Add extra diagnostic tests for "mismatched register size suffix"

Author: jthackray

llvm/test/MC/AArch64/SVE2p3/qshrn-diagnostics.s

@@ -13,6 +13,14 @@ sqrshrn z10.d, { z0.d, z1.d }, #1
 // CHECK-NEXT: sqrshrn z10.d, { z0.d, z1.d }, #1
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
+// --------------------------------------------------------------------------//
+// Mismatched register size suffix
+
+sqrshrn z0.b, { z0.h, z1.s }, #1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
+// CHECK-NEXT: sqrshrn z0.b, { z0.h, z1.s }, #1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
 // --------------------------------------------------------------------------//
 // Invalid operand for instruction
 
@@ -87,6 +95,14 @@ sqrshrun z10.b, { z1.h, z2.h }, #1
 // CHECK-NEXT: sqrshrun z10.b, { z1.h, z2.h }, #1
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
+// --------------------------------------------------------------------------//
+// Mismatched register size suffix
+
+sqrshrun z0.b, { z0.h, z1.s }, #1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
+// CHECK-NEXT: sqrshrun z0.b, { z0.h, z1.s }, #1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
 // --------------------------------------------------------------------------//
 // Negative tests for instructions that are incompatible with movprfx
 
@@ -109,6 +125,14 @@ sqshrn z10.d, { z0.d, z1.d }, #1
 // CHECK-NEXT: sqshrn z10.d, { z0.d, z1.d }, #1
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
+// --------------------------------------------------------------------------//
+// Mismatched register size suffix
+
+sqshrn z0.b, { z0.h, z1.s }, #1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
+// CHECK-NEXT: sqshrn z0.b, { z0.h, z1.s }, #1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
 // --------------------------------------------------------------------------//
 // Intermediate out of range
 
@@ -159,6 +183,14 @@ sqshrun z10.d, { z0.d, z1.d }, #1
 // CHECK-NEXT: sqshrun z10.d, { z0.d, z1.d }, #1
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
+// --------------------------------------------------------------------------//
+// Mismatched register size suffix
+
+sqshrun z0.b, { z0.h, z1.s }, #1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
+// CHECK-NEXT: sqshrun z0.b, { z0.h, z1.s }, #1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
 // --------------------------------------------------------------------------//
 // Intermediate out of range
 
@@ -209,6 +241,14 @@ uqrshrn z10.d, { z0.d, z1.d }, #1
 // CHECK-NEXT: uqrshrn z10.d, { z0.d, z1.d }, #1
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
+// --------------------------------------------------------------------------//
+// Mismatched register size suffix
+
+uqrshrn z0.b, { z0.h, z1.s }, #1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
+// CHECK-NEXT: uqrshrn z0.b, { z0.h, z1.s }, #1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
 // --------------------------------------------------------------------------//
 // Invalid operand for instruction
 
@@ -257,6 +297,14 @@ uqshrn z10.d, { z0.d, z1.d }, #1
 // CHECK-NEXT: uqshrn z10.d, { z0.d, z1.d }, #1
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
+// --------------------------------------------------------------------------//
+// Mismatched register size suffix
+
+uqshrn z0.b, { z0.h, z1.s }, #1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
+// CHECK-NEXT: uqshrn z0.b, { z0.h, z1.s }, #1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
 // --------------------------------------------------------------------------//
 // Intermediate out of range