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[RISCV] Update SiFive7's scheduling model on mask and data movement instructions (#160155)
Vector to scalar movement instructions, as well as mask instructions like vcpop and vfirst, should have a higher latency & occupancy on SiFive7. --------- Co-authored-by: Michael Maitland <[email protected]>
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‎llvm/lib/Target/RISCV/RISCVSchedSiFive7.td‎

Lines changed: 14 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -929,16 +929,16 @@ multiclass SiFive7WriteResBase<int VLEN,
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}
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// 15. Vector Mask Instructions
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// Simple mask logical
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foreach mx = SchedMxList in {
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defvar Cycles = SiFive7GetCyclesVMask<mx>.c;
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defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
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let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
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defm : LMULWriteResMX<"WriteVMALUV", [VCQ, VA1], mx, IsWorstCase>;
937-
defm : LMULWriteResMX<"WriteVMPopV", [VCQ, VA1], mx, IsWorstCase>;
938-
defm : LMULWriteResMX<"WriteVMFFSV", [VCQ, VA1], mx, IsWorstCase>;
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defm : LMULWriteResMX<"WriteVMSFSV", [VCQ, VA1], mx, IsWorstCase>;
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}
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}
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// Simple mask logical used in series
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foreach mx = SchedMxList in {
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defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
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defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
@@ -947,13 +947,23 @@ multiclass SiFive7WriteResBase<int VLEN,
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defm : LMULWriteResMX<"WriteVIdxV", [VCQ, VA1], mx, IsWorstCase>;
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}
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}
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// Mask reduction
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foreach mx = SchedMxList in {
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defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
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let Latency = 11, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, 3)] in {
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defm "" : LMULWriteResMX<"WriteVMFFSV", [VCQ, VA1], mx, IsWorstCase>;
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defm "" : LMULWriteResMX<"WriteVMPopV", [VCQ, VA1], mx, IsWorstCase>;
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}
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}
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// 16. Vector Permutation Instructions
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let Latency = 11, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, 3)] in {
961+
def : WriteRes<WriteVMovXS, [VCQ, VA1]>;
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def : WriteRes<WriteVMovFS, [VCQ, VA1]>;
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}
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let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, 1)] in {
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def : WriteRes<WriteVMovSX, [VCQ, VA1OrVA2]>;
954-
def : WriteRes<WriteVMovXS, [VCQ, VA1]>;
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def : WriteRes<WriteVMovSF, [VCQ, VA1OrVA2]>;
956-
def : WriteRes<WriteVMovFS, [VCQ, VA1]>;
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}
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foreach mx = SchedMxList in {
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defvar Cycles = SiFive7GetCyclesDefault<mx>.c;

‎llvm/test/tools/llvm-mca/RISCV/SiFive7/mask.s‎

Lines changed: 125 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,125 @@
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 -instruction-tables=full < %s | FileCheck %s
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vsetvli zero, zero, e32, m1, ta, ma
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vmslt.vv v0, v4, v20
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vmsle.vv v8, v4, v20
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vmsgt.vv v8, v20, v4
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vmsge.vv v8, v20, v4
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vmseq.vv v8, v4, v20
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vmsne.vv v8, v4, v20
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vmsltu.vv v8, v4, v20
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vmsleu.vv v8, v4, v20
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vmsgtu.vv v8, v20, v4
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vmsgeu.vv v8, v20, v4
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vmflt.vv v0, v4, v20
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vmfle.vv v8, v4, v20
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vmfgt.vv v8, v20, v4
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vmfge.vv v8, v20, v4
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vmfeq.vv v8, v4, v20
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vmfne.vv v8, v4, v20
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vmadc.vv v8, v4, v20
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vmsbc.vv v8, v4, v20
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vfirst.m a2, v4
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vpopc.m a2, v4
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viota.m v8, v4
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vmsbf.m v8, v4
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vmsif.m v8, v4
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vmsof.m v8, v4
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# CHECK: Resources:
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# CHECK-NEXT: [0] - VLEN512SiFive7FDiv:1
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# CHECK-NEXT: [1] - VLEN512SiFive7IDiv:1
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# CHECK-NEXT: [2] - VLEN512SiFive7PipeA:1
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# CHECK-NEXT: [3] - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB
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# CHECK-NEXT: [4] - VLEN512SiFive7PipeB:1
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# CHECK-NEXT: [5] - VLEN512SiFive7VA:1
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# CHECK-NEXT: [6] - VLEN512SiFive7VCQ:1
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# CHECK-NEXT: [7] - VLEN512SiFive7VL:1
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# CHECK-NEXT: [8] - VLEN512SiFive7VS:1
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK-NEXT: [7]: Bypass Latency
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# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
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# CHECK-NEXT: [9]: LLVM Opcode Name
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# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
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# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m1, ta, ma
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# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSLT_VV vmslt.vv v0, v4, v20
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# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSLE_VV vmsle.vv v8, v4, v20
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# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSLT_VV vmslt.vv v8, v4, v20
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# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSLE_VV vmsle.vv v8, v4, v20
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# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSEQ_VV vmseq.vv v8, v4, v20
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# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSNE_VV vmsne.vv v8, v4, v20
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# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSLTU_VV vmsltu.vv v8, v4, v20
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# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSLEU_VV vmsleu.vv v8, v4, v20
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# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSLTU_VV vmsltu.vv v8, v4, v20
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# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSLEU_VV vmsleu.vv v8, v4, v20
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# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMFLT_VV vmflt.vv v0, v4, v20
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# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMFLE_VV vmfle.vv v8, v4, v20
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# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMFLT_VV vmflt.vv v8, v4, v20
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# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMFLE_VV vmfle.vv v8, v4, v20
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# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMFEQ_VV vmfeq.vv v8, v4, v20
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# CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMFNE_VV vmfne.vv v8, v4, v20
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# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMADC_VV vmadc.vv v8, v4, v20
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# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSBC_VV vmsbc.vv v8, v4, v20
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# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA[1,4],VLEN512SiFive7VCQ VFIRST_M vfirst.m a2, v4
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# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA[1,4],VLEN512SiFive7VCQ VCPOP_M vcpop.m a2, v4
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# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VIOTA_M viota.m v8, v4
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# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VMSBF_M vmsbf.m v8, v4
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# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VMSIF_M vmsif.m v8, v4
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# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VMSOF_M vmsof.m v8, v4
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# CHECK: Resources:
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# CHECK-NEXT: [0] - VLEN512SiFive7FDiv
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# CHECK-NEXT: [1] - VLEN512SiFive7IDiv
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# CHECK-NEXT: [2] - VLEN512SiFive7PipeA
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# CHECK-NEXT: [3] - VLEN512SiFive7PipeB
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# CHECK-NEXT: [4] - VLEN512SiFive7VA
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# CHECK-NEXT: [5] - VLEN512SiFive7VCQ
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# CHECK-NEXT: [6] - VLEN512SiFive7VL
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# CHECK-NEXT: [7] - VLEN512SiFive7VS
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
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# CHECK-NEXT: - - 1.00 - 71.00 24.00 - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
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# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, ta, ma
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# CHECK-NEXT: - - - - 3.00 1.00 - - vmslt.vv v0, v4, v20
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# CHECK-NEXT: - - - - 3.00 1.00 - - vmsle.vv v8, v4, v20
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# CHECK-NEXT: - - - - 3.00 1.00 - - vmslt.vv v8, v4, v20
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# CHECK-NEXT: - - - - 3.00 1.00 - - vmsle.vv v8, v4, v20
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# CHECK-NEXT: - - - - 3.00 1.00 - - vmseq.vv v8, v4, v20
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# CHECK-NEXT: - - - - 3.00 1.00 - - vmsne.vv v8, v4, v20
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# CHECK-NEXT: - - - - 3.00 1.00 - - vmsltu.vv v8, v4, v20
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# CHECK-NEXT: - - - - 3.00 1.00 - - vmsleu.vv v8, v4, v20
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# CHECK-NEXT: - - - - 3.00 1.00 - - vmsltu.vv v8, v4, v20
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# CHECK-NEXT: - - - - 3.00 1.00 - - vmsleu.vv v8, v4, v20
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# CHECK-NEXT: - - - - 3.00 1.00 - - vmflt.vv v0, v4, v20
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# CHECK-NEXT: - - - - 3.00 1.00 - - vmfle.vv v8, v4, v20
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# CHECK-NEXT: - - - - 3.00 1.00 - - vmflt.vv v8, v4, v20
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# CHECK-NEXT: - - - - 3.00 1.00 - - vmfle.vv v8, v4, v20
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# CHECK-NEXT: - - - - 3.00 1.00 - - vmfeq.vv v8, v4, v20
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# CHECK-NEXT: - - - - 3.00 1.00 - - vmfne.vv v8, v4, v20
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# CHECK-NEXT: - - - - 3.00 1.00 - - vmadc.vv v8, v4, v20
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# CHECK-NEXT: - - - - 3.00 1.00 - - vmsbc.vv v8, v4, v20
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# CHECK-NEXT: - - - - 4.00 1.00 - - vfirst.m a2, v4
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# CHECK-NEXT: - - - - 4.00 1.00 - - vcpop.m a2, v4
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# CHECK-NEXT: - - - - 3.00 1.00 - - viota.m v8, v4
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# CHECK-NEXT: - - - - 2.00 1.00 - - vmsbf.m v8, v4
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# CHECK-NEXT: - - - - 2.00 1.00 - - vmsif.m v8, v4
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# CHECK-NEXT: - - - - 2.00 1.00 - - vmsof.m v8, v4

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