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[llvm] NFC: fix trivial typos in documents
Reviewers: hans, Jim Reviewed By: Jim Subscribers: jvesely, nhaehnle, mgorny, arphaman, bmahjour, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D73017
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‎llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst‎

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Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
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Overview
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========
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An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this document<amdgpu_syn_instructions>`.
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‎llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst‎

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Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
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Overview
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========
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An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this document<amdgpu_syn_instructions>`.
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‎llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst‎

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Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
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Overview
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An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this document<amdgpu_syn_instructions>`.
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‎llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst‎

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Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
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Overview
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An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this document<amdgpu_syn_instructions>`.
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‎llvm/docs/AMDGPU/AMDGPUAsmGFX900.rst‎

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Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
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Overview
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An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this document<amdgpu_syn_instructions>`.
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‎llvm/docs/AMDGPU/AMDGPUAsmGFX904.rst‎

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Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
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An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this document<amdgpu_syn_instructions>`.
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‎llvm/docs/AMDGPU/AMDGPUAsmGFX906.rst‎

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Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
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An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this document<amdgpu_syn_instructions>`.
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‎llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst‎

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Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
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An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this document<amdgpu_syn_instructions>`.
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‎llvm/docs/Atomics.rst‎

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There's two typical examples of this.
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Some CPUs support multiple instruction sets which can be swiched back and forth
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Some CPUs support multiple instruction sets which can be switched back and forth
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on function-call boundaries. For example, MIPS supports the MIPS16 ISA, which
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has a smaller instruction encoding than the usual MIPS32 ISA. ARM, similarly,
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has the Thumb ISA. In MIPS16 and earlier versions of Thumb, the atomic

‎llvm/docs/BigEndianNEON.rst‎

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The aim of this document is to explain the problem with NEON loads and stores, and the solution that has been implemented in LLVM.
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In this document the term "vector" refers to what the ARM ABI calls a "short vector", which is a sequence of items that can fit in a NEON register. This sequence can be 64 or 128 bits in length, and can constitute 8, 16, 32 or 64 bit items. This document refers to A64 instructions throughout, but is almost applicable to the A32/ARMv7 instruction sets also. The ABI format for passing vectors in A32 is sligtly different to A64. Apart from that, the same concepts apply.
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In this document the term "vector" refers to what the ARM ABI calls a "short vector", which is a sequence of items that can fit in a NEON register. This sequence can be 64 or 128 bits in length, and can constitute 8, 16, 32 or 64 bit items. This document refers to A64 instructions throughout, but is almost applicable to the A32/ARMv7 instruction sets also. The ABI format for passing vectors in A32 is slightly different to A64. Apart from that, the same concepts apply.
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Example: C-level intrinsics -> assembly
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