[AArch64] Disable Pre-RA Scheduler for Neoverse V2

We would like to disable the pre-RA machine scheduler for the Neoverse
V2 because we have a key workload that massively benefits from this (25%
uplift). Despite the machine scheduler being register pressure aware, it
results in spills for this workload. Disabling the scheduler seems a lot
more attractive than trying to tweak regalloc heuristics:
- We see no benefit of scheduling anyway on this big core, and have
  never seen this. I.e., when we added the V2 scheduling model, this
  wasn't for perf reasons, only to enable LLVM-MCA.
- Scheduling can consume significant compile-time, not resulting in any
  perf gains. This is a bad deal.

FWIW: the GCC folks realised the same not that long ago, and did exactly
the same, see also:
https://gcc.gnu.org/pipermail/gcc-patches/2024-October/667074.html

I guess other big cores could benefit from this too, but I would like
to leave that decision to folks with more experience on those cores, so
that's why I propose to change this for the V2 here only.

Numbers:
* We know the Eigen library is somewhat sensitive to scheduling, but
  I found one kernel to regress with ~2%, and another to improve with
  ~2%. They cancel each other out, and overall the result is neutral.
* SPEC FP and INT seem totally unaffected.
* LLVM test-suite: a little bit up and down, all within noise levels I
  think, so is neutral.
* Compile-time numbers: I see a geomean 3% improvement for the LLVM
  test-suite, and a very decent one for the sqlite amalgamation version.

I haven't looked at the post-RA scheduling, maybe that's interesting
as a follow up.

Author: sjoerdmeijer

llvm/lib/Target/AArch64/AArch64Features.td

@@ -669,6 +669,9 @@ def FeatureExynosCheapAsMoveHandling : SubtargetFeature<"exynos-cheap-as-move",
     "HasExynosCheapAsMoveHandling", "true",
     "Use Exynos specific handling of cheap instructions">;
 
+def FeatureDisablePreRAScheduler : SubtargetFeature<"use-prera-scheduler",
+    "DisablePreRAScheduler", "true", "Disable scheduling before register allocation">;
+
 def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
     "UsePostRAScheduler", "true", "Schedule again after register allocation">;
 

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -1173,7 +1173,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
 
   setStackPointerRegisterToSaveRestore(AArch64::SP);
 
-  setSchedulingPreference(Sched::Hybrid);
+  setSchedulingPreference(Subtarget->enableMachineScheduler() ? Sched::Hybrid
+                                                              : Sched::Source);
 
   EnableExtLdPromotion = true;
 

llvm/lib/Target/AArch64/AArch64Processors.td

@@ -540,6 +540,7 @@ def TuneNeoverseV2 : SubtargetFeature<"neoversev2", "ARMProcFamily", "NeoverseV2
                                       FeatureCmpBccFusion,
                                       FeatureFuseAdrpAdd,
                                       FeatureALULSLFast,
+                                      FeatureDisablePreRAScheduler,
                                       FeaturePostRAScheduler,
                                       FeatureEnableSelectOptimize,
                                       FeatureUseFixedOverScalableIfEqualCost,

llvm/lib/Target/AArch64/AArch64Subtarget.h

@@ -156,7 +156,9 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
   const LegalizerInfo *getLegalizerInfo() const override;
   const RegisterBankInfo *getRegBankInfo() const override;
   const Triple &getTargetTriple() const { return TargetTriple; }
-  bool enableMachineScheduler() const override { return true; }
+  bool enableMachineScheduler() const override {
+    return !disablePreRAScheduler();
+  }
   bool enablePostRAScheduler() const override { return usePostRAScheduler(); }
   bool enableSubRegLiveness() const override { return EnableSubregLiveness; }