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RamNalamothuRamNalamothu
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[llvm] Pass MachineInstr flags to storeRegToStackSlot/loadRegFromStackSlot (NFC)
This patch is in preparation to enable setting the MachineInstr::MIFlag flags, i.e. FrameSetup/FrameDestroy, on callee saved register spill/reload instructions in prologue/epilogue. This eventually helps in setting the prologue_end and epilogue_begin markers more accurately. The DWARF Spec in "6.4 Call Frame Information" says: The code that allocates space on the call frame stack and performs the save operation is called the subroutine’s prologue, and the code that performs the restore operation and deallocates the frame is called its epilogue. which means the callee saved register spills and reloads are part of prologue (a.k.a frame setup) and epilogue (a.k.a frame destruction), respectively. And, IIUC, LLVM backend uses FrameSetup/FrameDestroy flags to identify instructions that are part of call frame setup and destruction. In the trunk, while most targets consistently set FrameSetup/FrameDestroy on save/restore call frame information (CFI) instructions of callee saved registers, they do not consistently set those flags on the actual callee saved register spill/reload instructions. I believe this patch provides a clean mechanism to set FrameSetup/FrameDestroy flags on the actual callee saved register spill/reload instructions as needed. And, by having default argument of MachineInstr::NoFlags for Flags, this patch is a NFC. With this patch, the targets have to just pass FrameSetup/FrameDestroy flag to the storeRegToStackSlot/loadRegFromStackSlot calls from the target derived spillCalleeSavedRegisters and restoreCalleeSavedRegisters to set those flags on callee saved register spill/reload instructions. Also, this patch makes it very easy to set the source line information on callee saved register spill/reload instructions which is needed by the DwarfDebug.cpp implementation to set prologue_end and epilogue_begin markers more accurately. As per DwarfDebug.cpp implementation: prologue_end is the first known non-DBG_VALUE and non-FrameSetup location that marks the beginning of the function body epilogue_begin is the first FrameDestroy location that has been seen in the epilogue basic block With this patch, the targets have to just do the following to set the source line information on callee saved register spill/reload instructions, without hampering the LLVM's efforts to avoid adding source line information on the artificial code generated by the compiler. <Foo>InstrInfo::storeRegToStackSlot() { ... DebugLoc DL = Flags & MachineInstr::FrameSetup ? DebugLoc() : MBB.findDebugLoc(I); ... } <Foo>InstrInfo::loadRegFromStackSlot() { ... DebugLoc DL = Flags & MachineInstr::FrameDestroy ? MBB.findDebugLoc(I) : DebugLoc(); ... } While I understand this patch would break out-of-tree backend builds, I think it is in the right direction. One immediate use case that can benefit from this patch is fixing #120553 becomes simpler.
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‎llvm/include/llvm/CodeGen/TargetInstrInfo.h‎

Lines changed: 16 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1142,13 +1142,14 @@ class TargetInstrInfo : public MCInstrInfo {
11421142
/// register, \p VReg is the register being assigned. This additional register
11431143
/// argument is needed for certain targets when invoked from RegAllocFast to
11441144
/// map the spilled physical register to its virtual register. A null register
1145-
/// can be passed elsewhere.
1146-
virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
1147-
MachineBasicBlock::iterator MI,
1148-
Register SrcReg, bool isKill, int FrameIndex,
1149-
const TargetRegisterClass *RC,
1150-
const TargetRegisterInfo *TRI,
1151-
Register VReg) const {
1145+
/// can be passed elsewhere. The \p Flags is used to set appropriate machine
1146+
/// flags on the spill instruction e.g. FrameSetup flag on a callee saved
1147+
/// register spill instruction, part of prologue, during the frame lowering.
1148+
virtual void storeRegToStackSlot(
1149+
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
1150+
bool isKill, int FrameIndex, const TargetRegisterClass *RC,
1151+
const TargetRegisterInfo *TRI, Register VReg,
1152+
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const {
11521153
llvm_unreachable("Target didn't implement "
11531154
"TargetInstrInfo::storeRegToStackSlot!");
11541155
}
@@ -1160,13 +1161,14 @@ class TargetInstrInfo : public MCInstrInfo {
11601161
/// register, \p VReg is the register being assigned. This additional register
11611162
/// argument is needed for certain targets when invoked from RegAllocFast to
11621163
/// map the loaded physical register to its virtual register. A null register
1163-
/// can be passed elsewhere.
1164-
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
1165-
MachineBasicBlock::iterator MI,
1166-
Register DestReg, int FrameIndex,
1167-
const TargetRegisterClass *RC,
1168-
const TargetRegisterInfo *TRI,
1169-
Register VReg) const {
1164+
/// can be passed elsewhere. The \p Flags is used to set appropriate machine
1165+
/// flags on the spill instruction e.g. FrameDestroy flag on a callee saved
1166+
/// register reload instruction, part of epilogue, during the frame lowering.
1167+
virtual void loadRegFromStackSlot(
1168+
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,
1169+
int FrameIndex, const TargetRegisterClass *RC,
1170+
const TargetRegisterInfo *TRI, Register VReg,
1171+
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const {
11701172
llvm_unreachable("Target didn't implement "
11711173
"TargetInstrInfo::loadRegFromStackSlot!");
11721174
}

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp‎

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -5278,7 +5278,8 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
52785278
Register SrcReg, bool isKill, int FI,
52795279
const TargetRegisterClass *RC,
52805280
const TargetRegisterInfo *TRI,
5281-
Register VReg) const {
5281+
Register VReg,
5282+
MachineInstr::MIFlag Flags) const {
52825283
MachineFunction &MF = *MBB.getParent();
52835284
MachineFrameInfo &MFI = MF.getFrameInfo();
52845285

@@ -5445,12 +5446,10 @@ static void loadRegPairFromStackSlot(const TargetRegisterInfo &TRI,
54455446
.addMemOperand(MMO);
54465447
}
54475448

5448-
void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
5449-
MachineBasicBlock::iterator MBBI,
5450-
Register DestReg, int FI,
5451-
const TargetRegisterClass *RC,
5452-
const TargetRegisterInfo *TRI,
5453-
Register VReg) const {
5449+
void AArch64InstrInfo::loadRegFromStackSlot(
5450+
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg,
5451+
int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
5452+
Register VReg, MachineInstr::MIFlag Flags) const {
54545453
MachineFunction &MF = *MBB.getParent();
54555454
MachineFrameInfo &MFI = MF.getFrameInfo();
54565455
MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(MF, FI);

‎llvm/lib/Target/AArch64/AArch64InstrInfo.h‎

Lines changed: 11 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -347,18 +347,17 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
347347
bool KillSrc, bool RenamableDest = false,
348348
bool RenamableSrc = false) const override;
349349

350-
void storeRegToStackSlot(MachineBasicBlock &MBB,
351-
MachineBasicBlock::iterator MBBI, Register SrcReg,
352-
bool isKill, int FrameIndex,
353-
const TargetRegisterClass *RC,
354-
const TargetRegisterInfo *TRI,
355-
Register VReg) const override;
356-
357-
void loadRegFromStackSlot(MachineBasicBlock &MBB,
358-
MachineBasicBlock::iterator MBBI, Register DestReg,
359-
int FrameIndex, const TargetRegisterClass *RC,
360-
const TargetRegisterInfo *TRI,
361-
Register VReg) const override;
350+
void storeRegToStackSlot(
351+
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
352+
bool isKill, int FrameIndex, const TargetRegisterClass *RC,
353+
const TargetRegisterInfo *TRI, Register VReg,
354+
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
355+
356+
void loadRegFromStackSlot(
357+
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
358+
Register DestReg, int FrameIndex, const TargetRegisterClass *RC,
359+
const TargetRegisterInfo *TRI, Register VReg,
360+
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
362361

363362
// This tells target independent code that it is okay to pass instructions
364363
// with subreg operands to foldMemoryOperandImpl.

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1724,7 +1724,8 @@ static unsigned getVectorRegSpillSaveOpcode(Register Reg,
17241724
void SIInstrInfo::storeRegToStackSlot(
17251725
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
17261726
bool isKill, int FrameIndex, const TargetRegisterClass *RC,
1727-
const TargetRegisterInfo *TRI, Register VReg) const {
1727+
const TargetRegisterInfo *TRI, Register VReg,
1728+
MachineInstr::MIFlag Flags) const {
17281729
MachineFunction *MF = MBB.getParent();
17291730
SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
17301731
MachineFrameInfo &FrameInfo = MF->getFrameInfo();
@@ -1951,7 +1952,8 @@ void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
19511952
Register DestReg, int FrameIndex,
19521953
const TargetRegisterClass *RC,
19531954
const TargetRegisterInfo *TRI,
1954-
Register VReg) const {
1955+
Register VReg,
1956+
MachineInstr::MIFlag Flags) const {
19551957
MachineFunction *MF = MBB.getParent();
19561958
SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
19571959
MachineFrameInfo &FrameInfo = MF->getFrameInfo();

‎llvm/lib/Target/AMDGPU/SIInstrInfo.h‎

Lines changed: 11 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -280,18 +280,17 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
280280
MachineBasicBlock::iterator I, const DebugLoc &DL,
281281
Register SrcReg, int Value) const;
282282

283-
void storeRegToStackSlot(MachineBasicBlock &MBB,
284-
MachineBasicBlock::iterator MI, Register SrcReg,
285-
bool isKill, int FrameIndex,
286-
const TargetRegisterClass *RC,
287-
const TargetRegisterInfo *TRI,
288-
Register VReg) const override;
289-
290-
void loadRegFromStackSlot(MachineBasicBlock &MBB,
291-
MachineBasicBlock::iterator MI, Register DestReg,
292-
int FrameIndex, const TargetRegisterClass *RC,
293-
const TargetRegisterInfo *TRI,
294-
Register VReg) const override;
283+
void storeRegToStackSlot(
284+
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
285+
bool isKill, int FrameIndex, const TargetRegisterClass *RC,
286+
const TargetRegisterInfo *TRI, Register VReg,
287+
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
288+
289+
void loadRegFromStackSlot(
290+
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,
291+
int FrameIndex, const TargetRegisterClass *RC,
292+
const TargetRegisterInfo *TRI, Register VReg,
293+
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
295294

296295
bool expandPostRAPseudo(MachineInstr &MI) const override;
297296

‎llvm/lib/Target/ARC/ARCInstrInfo.cpp‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -294,7 +294,8 @@ void ARCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
294294
void ARCInstrInfo::storeRegToStackSlot(
295295
MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg,
296296
bool IsKill, int FrameIndex, const TargetRegisterClass *RC,
297-
const TargetRegisterInfo *TRI, Register VReg) const {
297+
const TargetRegisterInfo *TRI, Register VReg,
298+
MachineInstr::MIFlag Flags) const {
298299
DebugLoc DL = MBB.findDebugLoc(I);
299300
MachineFunction &MF = *MBB.getParent();
300301
MachineFrameInfo &MFI = MF.getFrameInfo();
@@ -323,7 +324,8 @@ void ARCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
323324
Register DestReg, int FrameIndex,
324325
const TargetRegisterClass *RC,
325326
const TargetRegisterInfo *TRI,
326-
Register VReg) const {
327+
Register VReg,
328+
MachineInstr::MIFlag Flags) const {
327329
DebugLoc DL = MBB.findDebugLoc(I);
328330
MachineFunction &MF = *MBB.getParent();
329331
MachineFrameInfo &MFI = MF.getFrameInfo();

‎llvm/lib/Target/ARC/ARCInstrInfo.h‎

Lines changed: 11 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -68,18 +68,17 @@ class ARCInstrInfo : public ARCGenInstrInfo {
6868
bool KillSrc, bool RenamableDest = false,
6969
bool RenamableSrc = false) const override;
7070

71-
void storeRegToStackSlot(MachineBasicBlock &MBB,
72-
MachineBasicBlock::iterator MI, Register SrcReg,
73-
bool IsKill, int FrameIndex,
74-
const TargetRegisterClass *RC,
75-
const TargetRegisterInfo *TRI,
76-
Register VReg) const override;
77-
78-
void loadRegFromStackSlot(MachineBasicBlock &MBB,
79-
MachineBasicBlock::iterator MI, Register DestReg,
80-
int FrameIndex, const TargetRegisterClass *RC,
81-
const TargetRegisterInfo *TRI,
82-
Register VReg) const override;
71+
void storeRegToStackSlot(
72+
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
73+
bool IsKill, int FrameIndex, const TargetRegisterClass *RC,
74+
const TargetRegisterInfo *TRI, Register VReg,
75+
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
76+
77+
void loadRegFromStackSlot(
78+
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,
79+
int FrameIndex, const TargetRegisterClass *RC,
80+
const TargetRegisterInfo *TRI, Register VReg,
81+
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
8382

8483
bool
8584
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;

‎llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp‎

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1118,7 +1118,8 @@ void ARMBaseInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
11181118
Register SrcReg, bool isKill, int FI,
11191119
const TargetRegisterClass *RC,
11201120
const TargetRegisterInfo *TRI,
1121-
Register VReg) const {
1121+
Register VReg,
1122+
MachineInstr::MIFlag Flags) const {
11221123
MachineFunction &MF = *MBB.getParent();
11231124
MachineFrameInfo &MFI = MF.getFrameInfo();
11241125
Align Alignment = MFI.getObjectAlign(FI);
@@ -1379,12 +1380,10 @@ Register ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
13791380
return false;
13801381
}
13811382

1382-
void ARMBaseInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1383-
MachineBasicBlock::iterator I,
1384-
Register DestReg, int FI,
1385-
const TargetRegisterClass *RC,
1386-
const TargetRegisterInfo *TRI,
1387-
Register VReg) const {
1383+
void ARMBaseInstrInfo::loadRegFromStackSlot(
1384+
MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg,
1385+
int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
1386+
Register VReg, MachineInstr::MIFlag Flags) const {
13881387
DebugLoc DL;
13891388
if (I != MBB.end()) DL = I->getDebugLoc();
13901389
MachineFunction &MF = *MBB.getParent();

‎llvm/lib/Target/ARM/ARMBaseInstrInfo.h‎

Lines changed: 11 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -212,18 +212,17 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
212212
bool KillSrc, bool RenamableDest = false,
213213
bool RenamableSrc = false) const override;
214214

215-
void storeRegToStackSlot(MachineBasicBlock &MBB,
216-
MachineBasicBlock::iterator MBBI, Register SrcReg,
217-
bool isKill, int FrameIndex,
218-
const TargetRegisterClass *RC,
219-
const TargetRegisterInfo *TRI,
220-
Register VReg) const override;
221-
222-
void loadRegFromStackSlot(MachineBasicBlock &MBB,
223-
MachineBasicBlock::iterator MBBI, Register DestReg,
224-
int FrameIndex, const TargetRegisterClass *RC,
225-
const TargetRegisterInfo *TRI,
226-
Register VReg) const override;
215+
void storeRegToStackSlot(
216+
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
217+
bool isKill, int FrameIndex, const TargetRegisterClass *RC,
218+
const TargetRegisterInfo *TRI, Register VReg,
219+
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
220+
221+
void loadRegFromStackSlot(
222+
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
223+
Register DestReg, int FrameIndex, const TargetRegisterClass *RC,
224+
const TargetRegisterInfo *TRI, Register VReg,
225+
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
227226

228227
bool expandPostRAPseudo(MachineInstr &MI) const override;
229228

‎llvm/lib/Target/ARM/Thumb1InstrInfo.cpp‎

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -117,7 +117,8 @@ void Thumb1InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
117117
Register SrcReg, bool isKill, int FI,
118118
const TargetRegisterClass *RC,
119119
const TargetRegisterInfo *TRI,
120-
Register VReg) const {
120+
Register VReg,
121+
MachineInstr::MIFlag Flags) const {
121122
assert((RC == &ARM::tGPRRegClass ||
122123
(SrcReg.isPhysical() && isARMLowRegister(SrcReg))) &&
123124
"Unknown regclass!");
@@ -141,12 +142,10 @@ void Thumb1InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
141142
}
142143
}
143144

144-
void Thumb1InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
145-
MachineBasicBlock::iterator I,
146-
Register DestReg, int FI,
147-
const TargetRegisterClass *RC,
148-
const TargetRegisterInfo *TRI,
149-
Register VReg) const {
145+
void Thumb1InstrInfo::loadRegFromStackSlot(
146+
MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg,
147+
int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
148+
Register VReg, MachineInstr::MIFlag Flags) const {
150149
assert((RC->hasSuperClassEq(&ARM::tGPRRegClass) ||
151150
(DestReg.isPhysical() && isARMLowRegister(DestReg))) &&
152151
"Unknown regclass!");

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