[PowerPC] Use the same lowering rule for vector rounding instructions

They should have the same lowering rule.

Author: paperchalice

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

@@ -1033,17 +1033,17 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
       // so we can only code-gen them with fpexcept.ignore.
       setOperationAction(ISD::STRICT_FNEARBYINT, MVT::f64, Custom);
       setOperationAction(ISD::STRICT_FNEARBYINT, MVT::f32, Custom);
+      setOperationAction(ISD::STRICT_FNEARBYINT, MVT::v2f64, Custom);
+      setOperationAction(ISD::STRICT_FNEARBYINT, MVT::v4f32, Custom);
 
       setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
       setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
       setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
-      setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
       setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
       setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
       setOperationAction(ISD::FROUND, MVT::f64, Legal);
       setOperationAction(ISD::FRINT, MVT::f64, Legal);
 
-      setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
       setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
       setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
       setOperationAction(ISD::FROUND, MVT::f32, Legal);

llvm/test/CodeGen/PowerPC/vec_rounding.ll

@@ -1,4 +1,5 @@
 ; RUN: llc -verify-machineinstrs -mcpu=pwr6 -mattr=+altivec < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=ppc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=NO-VSX
 
 ; Check vector round to single-precision toward -infinity (vrfim)
 ; instruction generation using Altivec.
@@ -81,6 +82,9 @@ define <2 x double> @nearbyint_v2f64(<2 x double> %p)
 ; CHECK-LABEL: nearbyint_v2f64:
 ; CHECK: bl nearbyint
 ; CHECK: bl nearbyint
+; NO-VSX-LABEL: nearbyint_v2f64:
+; NO-VSX: bl nearbyint
+; NO-VSX: bl nearbyint
 
 declare <4 x double> @llvm.nearbyint.v4f64(<4 x double> %p)
 define <4 x double> @nearbyint_v4f64(<4 x double> %p)
@@ -93,7 +97,11 @@ define <4 x double> @nearbyint_v4f64(<4 x double> %p)
 ; CHECK: bl nearbyint
 ; CHECK: bl nearbyint
 ; CHECK: bl nearbyint
-
+; NO-VSX-LABEL: nearbyint_v4f64:
+; NO-VSX: bl nearbyint
+; NO-VSX: bl nearbyint
+; NO-VSX: bl nearbyint
+; NO-VSX: bl nearbyint
 
 declare <4 x float> @llvm.floor.v4f32(<4 x float> %p)
 define <4 x float> @floor_v4f32(<4 x float> %p)