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davemgreendavemgreen
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Move into findValueFromDef
This now passes the type of the Reg required through to the ArtifactFinder and includes #119850. Most of the tests are just changing because they use IMPLICIT_DEF for the input. Most look OK to me, in that they are just changing `<complex legalization of implicitdef> + operations` to `implicitdef + operations`, as in ``` ; VI-LABEL: name: test_ffloor_v3s16 - ; VI: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF - ; VI-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF]](<4 x s16>) - ; VI-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>) - ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32) - ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; VI-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) - ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) - ; VI-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>) - ; VI-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](s32) - ; VI-NEXT: [[FFLOOR:%[0-9]+]]:_(s16) = G_FFLOOR [[TRUNC]] - ; VI-NEXT: [[FFLOOR1:%[0-9]+]]:_(s16) = G_FFLOOR [[TRUNC1]] - ; VI-NEXT: [[FFLOOR2:%[0-9]+]]:_(s16) = G_FFLOOR [[TRUNC2]] + ; VI: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF + ; VI-NEXT: [[FFLOOR:%[0-9]+]]:_(s16) = G_FFLOOR [[DEF]] + ; VI-NEXT: [[FFLOOR1:%[0-9]+]]:_(s16) = G_FFLOOR [[DEF]] + ; VI-NEXT: [[FFLOOR2:%[0-9]+]]:_(s16) = G_FFLOOR [[DEF]] ``` If any of these do look like a problem then let me know. I can try and define the inputs better if we can come up with a way to do that (many are G_IMPLICIT_DEF presumably because of the types involved). One Mips test has an extra mov in one of the tests from a COPY of undef. Some of the tests are now folding ZExt(IMPLICIT_DEF) to 0 which loses information about the undef bits but would likely have been done anyway.
1 parent 0517bf9 commit f0e5029

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14 files changed

+391
-203
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14 files changed

+391
-203
lines changed

‎llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h‎

Lines changed: 38 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,7 @@ class LegalizationArtifactCombiner {
7070
// aext(trunc x) - > aext/copy/trunc x
7171
Register TruncSrc;
7272
if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) {
73-
LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
73+
LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI);
7474
if (MRI.getType(DstReg) == MRI.getType(TruncSrc))
7575
replaceRegOrBuildCopy(DstReg, TruncSrc, MRI, Builder, UpdatedDefs,
7676
Observer);
@@ -136,7 +136,7 @@ class LegalizationArtifactCombiner {
136136
if (isInstUnsupported({TargetOpcode::G_AND, {DstTy}}) ||
137137
isConstantUnsupported(DstTy))
138138
return false;
139-
LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
139+
LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI);
140140
LLT SrcTy = MRI.getType(SrcReg);
141141
APInt MaskVal = APInt::getAllOnes(SrcTy.getScalarSizeInBits());
142142
if (SextSrc && (DstTy != MRI.getType(SextSrc)))
@@ -207,7 +207,7 @@ class LegalizationArtifactCombiner {
207207
LLT DstTy = MRI.getType(DstReg);
208208
if (isInstUnsupported({TargetOpcode::G_SEXT_INREG, {DstTy}}))
209209
return false;
210-
LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
210+
LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI);
211211
LLT SrcTy = MRI.getType(SrcReg);
212212
uint64_t SizeInBits = SrcTy.getScalarSizeInBits();
213213
if (DstTy != MRI.getType(TruncSrc))
@@ -356,11 +356,11 @@ class LegalizationArtifactCombiner {
356356
// trunc(ext x) -> x
357357
ArtifactValueFinder Finder(MRI, Builder, LI);
358358
if (Register FoundReg =
359-
Finder.findValueFromDef(DstReg, 0, DstTy.getSizeInBits())) {
359+
Finder.findValueFromDef(DstReg, 0, DstTy.getSizeInBits(), DstTy)) {
360360
LLT FoundRegTy = MRI.getType(FoundReg);
361361
if (DstTy == FoundRegTy) {
362362
LLVM_DEBUG(dbgs() << ".. Combine G_TRUNC(G_[S,Z,ANY]EXT/G_TRUNC...): "
363-
<< MI;);
363+
<< MI);
364364

365365
replaceRegOrBuildCopy(DstReg, FoundReg, MRI, Builder, UpdatedDefs,
366366
Observer);
@@ -392,7 +392,7 @@ class LegalizationArtifactCombiner {
392392
// G_ANYEXT (G_IMPLICIT_DEF) -> G_IMPLICIT_DEF
393393
if (!isInstLegal({TargetOpcode::G_IMPLICIT_DEF, {DstTy}}))
394394
return false;
395-
LLVM_DEBUG(dbgs() << ".. Combine G_ANYEXT(G_IMPLICIT_DEF): " << MI;);
395+
LLVM_DEBUG(dbgs() << ".. Combine G_ANYEXT(G_IMPLICIT_DEF): " << MI);
396396
auto Impl = Builder.buildUndef(DstTy);
397397
replaceRegOrBuildCopy(DstReg, Impl.getReg(0), MRI, Builder, UpdatedDefs,
398398
Observer);
@@ -402,7 +402,7 @@ class LegalizationArtifactCombiner {
402402
// bits will be 0 for G_ZEXT and 0/1 for the G_SEXT.
403403
if (isConstantUnsupported(DstTy))
404404
return false;
405-
LLVM_DEBUG(dbgs() << ".. Combine G_[SZ]EXT(G_IMPLICIT_DEF): " << MI;);
405+
LLVM_DEBUG(dbgs() << ".. Combine G_[SZ]EXT(G_IMPLICIT_DEF): " << MI);
406406
auto Cnst = Builder.buildConstant(DstTy, 0);
407407
replaceRegOrBuildCopy(DstReg, Cnst.getReg(0), MRI, Builder, UpdatedDefs,
408408
Observer);
@@ -641,10 +641,11 @@ class LegalizationArtifactCombiner {
641641
Register SrcReg = Concat.getReg(StartSrcIdx);
642642
if (InRegOffset == 0 && Size == SrcSize) {
643643
CurrentBest = SrcReg;
644-
return findValueFromDefImpl(SrcReg, 0, Size);
644+
return findValueFromDefImpl(SrcReg, 0, Size, MRI.getType(SrcReg));
645645
}
646646

647-
return findValueFromDefImpl(SrcReg, InRegOffset, Size);
647+
return findValueFromDefImpl(SrcReg, InRegOffset, Size,
648+
MRI.getType(SrcReg));
648649
}
649650

650651
/// Given an build_vector op \p BV and a start bit and size, try to find
@@ -759,15 +760,17 @@ class LegalizationArtifactCombiner {
759760
if (EndBit <= InsertOffset || InsertedEndBit <= StartBit) {
760761
SrcRegToUse = ContainerSrcReg;
761762
NewStartBit = StartBit;
762-
return findValueFromDefImpl(SrcRegToUse, NewStartBit, Size);
763+
return findValueFromDefImpl(SrcRegToUse, NewStartBit, Size,
764+
MRI.getType(SrcRegToUse));
763765
}
764766
if (InsertOffset <= StartBit && EndBit <= InsertedEndBit) {
765767
SrcRegToUse = InsertedReg;
766768
NewStartBit = StartBit - InsertOffset;
767769
if (NewStartBit == 0 &&
768770
Size == MRI.getType(SrcRegToUse).getSizeInBits())
769771
CurrentBest = SrcRegToUse;
770-
return findValueFromDefImpl(SrcRegToUse, NewStartBit, Size);
772+
return findValueFromDefImpl(SrcRegToUse, NewStartBit, Size,
773+
MRI.getType(SrcRegToUse));
771774
}
772775
// The bit range spans both the inserted and container regions.
773776
return Register();
@@ -799,7 +802,7 @@ class LegalizationArtifactCombiner {
799802

800803
if (StartBit == 0 && SrcType.getSizeInBits() == Size)
801804
CurrentBest = SrcReg;
802-
return findValueFromDefImpl(SrcReg, StartBit, Size);
805+
return findValueFromDefImpl(SrcReg, StartBit, Size, SrcType);
803806
}
804807

805808
/// Given an G_TRUNC op \p MI and a start bit and size, try to find
@@ -819,14 +822,14 @@ class LegalizationArtifactCombiner {
819822
if (!SrcType.isScalar())
820823
return CurrentBest;
821824

822-
return findValueFromDefImpl(SrcReg, StartBit, Size);
825+
return findValueFromDefImpl(SrcReg, StartBit, Size, SrcType);
823826
}
824827

825828
/// Internal implementation for findValueFromDef(). findValueFromDef()
826829
/// initializes some data like the CurrentBest register, which this method
827830
/// and its callees rely upon.
828831
Register findValueFromDefImpl(Register DefReg, unsigned StartBit,
829-
unsigned Size) {
832+
unsigned Size, LLT DstTy) {
830833
std::optional<DefinitionAndSourceRegister> DefSrcReg =
831834
getDefSrcRegIgnoringCopies(DefReg, MRI);
832835
MachineInstr *Def = DefSrcReg->MI;
@@ -847,7 +850,7 @@ class LegalizationArtifactCombiner {
847850
}
848851
Register SrcReg = Def->getOperand(Def->getNumOperands() - 1).getReg();
849852
Register SrcOriginReg =
850-
findValueFromDefImpl(SrcReg, StartBit + DefStartBit, Size);
853+
findValueFromDefImpl(SrcReg, StartBit + DefStartBit, Size, DstTy);
851854
if (SrcOriginReg)
852855
return SrcOriginReg;
853856
// Failed to find a further value. If the StartBit and Size perfectly
@@ -868,6 +871,12 @@ class LegalizationArtifactCombiner {
868871
case TargetOpcode::G_ZEXT:
869872
case TargetOpcode::G_ANYEXT:
870873
return findValueFromExt(*Def, StartBit, Size);
874+
case TargetOpcode::G_IMPLICIT_DEF: {
875+
if (MRI.getType(DefReg) == DstTy)
876+
return DefReg;
877+
MIB.setInstrAndDebugLoc(*Def);
878+
return MIB.buildUndef(DstTy).getReg(0);
879+
}
871880
default:
872881
return CurrentBest;
873882
}
@@ -882,10 +891,10 @@ class LegalizationArtifactCombiner {
882891
/// at position \p StartBit with size \p Size.
883892
/// \returns a register with the requested size, or an empty Register if no
884893
/// better value could be found.
885-
Register findValueFromDef(Register DefReg, unsigned StartBit,
886-
unsigned Size) {
894+
Register findValueFromDef(Register DefReg, unsigned StartBit, unsigned Size,
895+
LLT DstTy) {
887896
CurrentBest = Register();
888-
Register FoundReg = findValueFromDefImpl(DefReg, StartBit, Size);
897+
Register FoundReg = findValueFromDefImpl(DefReg, StartBit, Size, DstTy);
889898
return FoundReg != DefReg ? FoundReg : Register();
890899
}
891900

@@ -904,7 +913,8 @@ class LegalizationArtifactCombiner {
904913
DeadDefs[DefIdx] = true;
905914
continue;
906915
}
907-
Register FoundVal = findValueFromDef(DefReg, 0, DestTy.getSizeInBits());
916+
Register FoundVal =
917+
findValueFromDef(DefReg, 0, DestTy.getSizeInBits(), DestTy);
908918
if (!FoundVal)
909919
continue;
910920
if (MRI.getType(FoundVal) != DestTy)
@@ -923,7 +933,7 @@ class LegalizationArtifactCombiner {
923933

924934
GUnmerge *findUnmergeThatDefinesReg(Register Reg, unsigned Size,
925935
unsigned &DefOperandIdx) {
926-
if (Register Def = findValueFromDefImpl(Reg, 0, Size)) {
936+
if (Register Def = findValueFromDefImpl(Reg, 0, Size, MRI.getType(Reg))) {
927937
if (auto *Unmerge = dyn_cast<GUnmerge>(MRI.getVRegDef(Def))) {
928938
DefOperandIdx =
929939
Unmerge->findRegisterDefOperandIdx(Def, /*TRI=*/nullptr);
@@ -1074,17 +1084,6 @@ class LegalizationArtifactCombiner {
10741084

10751085
Builder.setInstrAndDebugLoc(MI);
10761086

1077-
if (SrcDef->getOpcode() == TargetOpcode::G_IMPLICIT_DEF) {
1078-
auto Undef = Builder.buildUndef(DestTy);
1079-
for (unsigned I = 0; I != NumDefs; ++I) {
1080-
Register Def = MI.getReg(I);
1081-
replaceRegOrBuildCopy(Def, Undef.getReg(0), MRI, Builder, UpdatedDefs,
1082-
Observer);
1083-
}
1084-
markInstAndDefDead(MI, *SrcDef, DeadInsts, SrcDefIdx);
1085-
return true;
1086-
}
1087-
10881087
ArtifactValueFinder Finder(MRI, Builder, LI);
10891088
if (Finder.tryCombineUnmergeDefs(MI, Observer, UpdatedDefs)) {
10901089
markInstAndDefDead(MI, *SrcDef, DeadInsts, SrcDefIdx);
@@ -1294,12 +1293,19 @@ class LegalizationArtifactCombiner {
12941293
// for N >= %2.getSizeInBits() / 2
12951294
// %3 = G_EXTRACT %1, (N - %0.getSizeInBits()
12961295

1296+
Register DstReg = MI.getOperand(0).getReg();
12971297
Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg());
12981298
MachineInstr *MergeI = MRI.getVRegDef(SrcReg);
1299+
if (MergeI && MergeI->getOpcode() == TargetOpcode::G_IMPLICIT_DEF) {
1300+
Builder.setInstrAndDebugLoc(MI);
1301+
Builder.buildUndef(DstReg);
1302+
UpdatedDefs.push_back(DstReg);
1303+
markInstAndDefDead(MI, *MergeI, DeadInsts);
1304+
return true;
1305+
}
12991306
if (!MergeI || !isa<GMergeLikeInstr>(MergeI))
13001307
return false;
13011308

1302-
Register DstReg = MI.getOperand(0).getReg();
13031309
LLT DstTy = MRI.getType(DstReg);
13041310
LLT SrcTy = MRI.getType(SrcReg);
13051311

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir‎

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -290,11 +290,8 @@ body: |
290290
; CHECK-LABEL: name: s3_from_s35
291291
; CHECK: liveins: $w0
292292
; CHECK-NEXT: {{ $}}
293-
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
294-
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[DEF]](s64)
295-
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
296-
; CHECK-NEXT: %ext:_(s32) = G_AND [[TRUNC]], [[C]]
297-
; CHECK-NEXT: $w0 = COPY %ext(s32)
293+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
294+
; CHECK-NEXT: $w0 = COPY [[C]](s32)
298295
; CHECK-NEXT: RET_ReallyLR implicit $w0
299296
%val:_(s35) = G_IMPLICIT_DEF
300297
%extract:_(s3) = G_EXTRACT %val, 0

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir‎

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -545,15 +545,18 @@ body: |
545545
; CHECK-LABEL: name: store_6xs64
546546
; CHECK: liveins: $x0
547547
; CHECK-NEXT: {{ $}}
548-
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
548+
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
549+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[DEF]](s64), [[DEF]](s64)
550+
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[DEF]](s64), [[DEF]](s64)
551+
; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[DEF]](s64), [[DEF]](s64)
549552
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
550-
; CHECK-NEXT: G_STORE [[DEF]](<2 x s64>), %ptr(p0) :: (store (<2 x s64>))
553+
; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), %ptr(p0) :: (store (<2 x s64>))
551554
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
552555
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C]](s64)
553-
; CHECK-NEXT: G_STORE [[DEF]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
556+
; CHECK-NEXT: G_STORE [[BUILD_VECTOR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
554557
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
555558
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C1]](s64)
556-
; CHECK-NEXT: G_STORE [[DEF]](<2 x s64>), [[PTR_ADD1]](p0) :: (store (<2 x s64>) into unknown-address + 32)
559+
; CHECK-NEXT: G_STORE [[BUILD_VECTOR2]](<2 x s64>), [[PTR_ADD1]](p0) :: (store (<2 x s64>) into unknown-address + 32)
557560
; CHECK-NEXT: RET_ReallyLR
558561
%val:_(<6 x s64>) = G_IMPLICIT_DEF
559562
%ptr:_(p0) = COPY $x0

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -289,28 +289,28 @@ body: |
289289
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4100
290290
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), %w0(s32), [[C]]
291291
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ICMP2]], 1
292-
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
292+
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
293+
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
293294
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
294295
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
295-
; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C1]](s64)
296+
; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s16>) = G_INSERT_VECTOR_ELT [[DEF1]], [[TRUNC]](s16), [[C1]](s64)
296297
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[IVEC]](<4 x s16>)
297298
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[UV]](s16)
298299
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[UV1]](s16)
299300
; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[UV2]](s16)
300301
; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(s8) = G_TRUNC [[UV3]](s16)
301-
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
302-
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR [[TRUNC1]](s8), [[TRUNC2]](s8), [[TRUNC3]](s8), [[TRUNC4]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8)
303-
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
304-
; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(s8) = G_TRUNC [[DEF2]](s16)
305-
; CHECK-NEXT: [[TRUNC6:%[0-9]+]]:_(s8) = G_TRUNC [[DEF2]](s16)
306-
; CHECK-NEXT: [[TRUNC7:%[0-9]+]]:_(s8) = G_TRUNC [[DEF2]](s16)
307-
; CHECK-NEXT: [[TRUNC8:%[0-9]+]]:_(s8) = G_TRUNC [[DEF2]](s16)
308-
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR [[TRUNC5]](s8), [[TRUNC6]](s8), [[TRUNC7]](s8), [[TRUNC8]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8)
302+
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
303+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR [[TRUNC1]](s8), [[TRUNC2]](s8), [[TRUNC3]](s8), [[TRUNC4]](s8), [[DEF2]](s8), [[DEF2]](s8), [[DEF2]](s8), [[DEF2]](s8)
304+
; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s16)
305+
; CHECK-NEXT: [[TRUNC6:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s16)
306+
; CHECK-NEXT: [[TRUNC7:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s16)
307+
; CHECK-NEXT: [[TRUNC8:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s16)
308+
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR [[TRUNC5]](s8), [[TRUNC6]](s8), [[TRUNC7]](s8), [[TRUNC8]](s8), [[DEF2]](s8), [[DEF2]](s8), [[DEF2]](s8), [[DEF2]](s8)
309309
; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<8 x s8>) = G_SHUFFLE_VECTOR [[BUILD_VECTOR]](<8 x s8>), [[BUILD_VECTOR1]], shufflemask(0, 0, 0, 0, undef, undef, undef, undef)
310310
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
311311
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<8 x s16>) = G_ANYEXT [[SHUF]](<8 x s8>)
312312
; CHECK-NEXT: [[UV4:%[0-9]+]]:_(<4 x s16>), [[UV5:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[ANYEXT]](<8 x s16>)
313-
; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8)
313+
; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[DEF2]](s8), [[DEF2]](s8), [[DEF2]](s8), [[DEF2]](s8)
314314
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(<8 x s16>) = G_ANYEXT [[BUILD_VECTOR2]](<8 x s8>)
315315
; CHECK-NEXT: [[UV6:%[0-9]+]]:_(<4 x s16>), [[UV7:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[ANYEXT1]](<8 x s16>)
316316
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x s16>) = G_XOR [[UV4]], [[UV6]]

‎llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-trunc.mir‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -137,10 +137,10 @@ body: |
137137
bb.0:
138138
; Test that trunc(trunc) is combined to a single trunc
139139
; CHECK-LABEL: name: trunc_trunc
140-
; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
141-
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[DEF]](s64)
140+
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $sgpr0_sgpr1
141+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
142142
; CHECK-NEXT: $vgpr0 = COPY [[TRUNC]](s32)
143-
%0:_(s64) = G_IMPLICIT_DEF
143+
%0:_(s64) = COPY $sgpr0_sgpr1
144144
%1:_(s48) = G_TRUNC %0
145145
%2:_(s32) = G_TRUNC %1
146146
$vgpr0 = COPY %2

‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -241,8 +241,8 @@ body: |
241241
; GFX7-LABEL: name: test_fcmp_v3s32
242242
; GFX7: liveins: $vgpr0_vgpr1_vgpr2
243243
; GFX7-NEXT: {{ $}}
244-
; GFX7-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
245244
; GFX7-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
245+
; GFX7-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
246246
; GFX7-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
247247
; GFX7-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[DEF]](s32), [[UV]]
248248
; GFX7-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[DEF]](s32), [[UV1]]
@@ -256,8 +256,8 @@ body: |
256256
; GFX8-LABEL: name: test_fcmp_v3s32
257257
; GFX8: liveins: $vgpr0_vgpr1_vgpr2
258258
; GFX8-NEXT: {{ $}}
259-
; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
260259
; GFX8-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
260+
; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
261261
; GFX8-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
262262
; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[DEF]](s32), [[UV]]
263263
; GFX8-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[DEF]](s32), [[UV1]]
@@ -271,8 +271,8 @@ body: |
271271
; GFX9-LABEL: name: test_fcmp_v3s32
272272
; GFX9: liveins: $vgpr0_vgpr1_vgpr2
273273
; GFX9-NEXT: {{ $}}
274-
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
275274
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
275+
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
276276
; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
277277
; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[DEF]](s32), [[UV]]
278278
; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[DEF]](s32), [[UV1]]

‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -300,8 +300,8 @@ body: |
300300
; GFX7-LABEL: name: test_icmp_v3s32
301301
; GFX7: liveins: $vgpr0_vgpr1_vgpr2
302302
; GFX7-NEXT: {{ $}}
303-
; GFX7-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
304303
; GFX7-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
304+
; GFX7-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
305305
; GFX7-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
306306
; GFX7-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[DEF]](s32), [[UV]]
307307
; GFX7-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[DEF]](s32), [[UV1]]
@@ -319,8 +319,8 @@ body: |
319319
; GFX8-LABEL: name: test_icmp_v3s32
320320
; GFX8: liveins: $vgpr0_vgpr1_vgpr2
321321
; GFX8-NEXT: {{ $}}
322-
; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
323322
; GFX8-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
323+
; GFX8-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
324324
; GFX8-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
325325
; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[DEF]](s32), [[UV]]
326326
; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[DEF]](s32), [[UV1]]
@@ -338,8 +338,8 @@ body: |
338338
; GFX9-LABEL: name: test_icmp_v3s32
339339
; GFX9: liveins: $vgpr0_vgpr1_vgpr2
340340
; GFX9-NEXT: {{ $}}
341-
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
342341
; GFX9-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
342+
; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
343343
; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
344344
; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[DEF]](s32), [[UV]]
345345
; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[DEF]](s32), [[UV1]]

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