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arsenmarsenm
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AMDGPU: Select basic interp directly from intrinsics
llvm-svn: 375457
1 parent 8c6913a commit ef9a027

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5 files changed

+29
-57
lines changed

5 files changed

+29
-57
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp‎

Lines changed: 13 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -563,15 +563,26 @@ static bool hasSourceMods(const SDNode *N) {
563563
case ISD::FREM:
564564
case ISD::INLINEASM:
565565
case ISD::INLINEASM_BR:
566-
case AMDGPUISD::INTERP_P1:
567-
case AMDGPUISD::INTERP_P2:
568566
case AMDGPUISD::DIV_SCALE:
567+
case ISD::INTRINSIC_W_CHAIN:
569568

570569
// TODO: Should really be looking at the users of the bitcast. These are
571570
// problematic because bitcasts are used to legalize all stores to integer
572571
// types.
573572
case ISD::BITCAST:
574573
return false;
574+
case ISD::INTRINSIC_WO_CHAIN: {
575+
switch (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue()) {
576+
case Intrinsic::amdgcn_interp_p1:
577+
case Intrinsic::amdgcn_interp_p2:
578+
case Intrinsic::amdgcn_interp_mov:
579+
case Intrinsic::amdgcn_interp_p1_f16:
580+
case Intrinsic::amdgcn_interp_p2_f16:
581+
return false;
582+
default:
583+
return true;
584+
}
585+
}
575586
default:
576587
return true;
577588
}
@@ -4283,9 +4294,6 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
42834294
NODE_NAME_CASE(KILL)
42844295
NODE_NAME_CASE(DUMMY_CHAIN)
42854296
case AMDGPUISD::FIRST_MEM_OPCODE_NUMBER: break;
4286-
NODE_NAME_CASE(INTERP_MOV)
4287-
NODE_NAME_CASE(INTERP_P1)
4288-
NODE_NAME_CASE(INTERP_P2)
42894297
NODE_NAME_CASE(INTERP_P1LL_F16)
42904298
NODE_NAME_CASE(INTERP_P1LV_F16)
42914299
NODE_NAME_CASE(INTERP_P2_F16)

‎llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -476,9 +476,6 @@ enum NodeType : unsigned {
476476
BUILD_VERTICAL_VECTOR,
477477
/// Pointer to the start of the shader's constant data.
478478
CONST_DATA_PTR,
479-
INTERP_MOV,
480-
INTERP_P1,
481-
INTERP_P2,
482479
INTERP_P1LL_F16,
483480
INTERP_P1LV_F16,
484481
INTERP_P2_F16,

‎llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td‎

Lines changed: 0 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -329,18 +329,6 @@ def AMDGPUfdot2 : SDNode<"AMDGPUISD::FDOT2",
329329

330330
def AMDGPUperm : SDNode<"AMDGPUISD::PERM", AMDGPUDTIntTernaryOp, []>;
331331

332-
def AMDGPUinterp_mov : SDNode<"AMDGPUISD::INTERP_MOV",
333-
SDTypeProfile<1, 3, [SDTCisFP<0>]>,
334-
[SDNPInGlue]>;
335-
336-
def AMDGPUinterp_p1 : SDNode<"AMDGPUISD::INTERP_P1",
337-
SDTypeProfile<1, 3, [SDTCisFP<0>]>,
338-
[SDNPInGlue, SDNPOutGlue]>;
339-
340-
def AMDGPUinterp_p2 : SDNode<"AMDGPUISD::INTERP_P2",
341-
SDTypeProfile<1, 4, [SDTCisFP<0>]>,
342-
[SDNPInGlue]>;
343-
344332
def AMDGPUinterp_p1ll_f16 : SDNode<"AMDGPUISD::INTERP_P1LL_F16",
345333
SDTypeProfile<1, 7, [SDTCisFP<0>]>,
346334
[SDNPInGlue, SDNPOutGlue]>;

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp‎

Lines changed: 10 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -5876,36 +5876,21 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
58765876
}
58775877
case Intrinsic::amdgcn_fdiv_fast:
58785878
return lowerFDIV_FAST(Op, DAG);
5879-
case Intrinsic::amdgcn_interp_mov: {
5880-
SDValue ToM0 = DAG.getCopyToReg(DAG.getEntryNode(), DL, AMDGPU::M0,
5881-
Op.getOperand(4), SDValue());
5882-
return DAG.getNode(AMDGPUISD::INTERP_MOV, DL, MVT::f32, Op.getOperand(1),
5883-
Op.getOperand(2), Op.getOperand(3), ToM0.getValue(1));
5884-
}
5885-
case Intrinsic::amdgcn_interp_p1: {
5886-
SDValue ToM0 = DAG.getCopyToReg(DAG.getEntryNode(), DL, AMDGPU::M0,
5887-
Op.getOperand(4), SDValue());
5888-
return DAG.getNode(AMDGPUISD::INTERP_P1, DL, MVT::f32, Op.getOperand(1),
5889-
Op.getOperand(2), Op.getOperand(3), ToM0.getValue(1));
5890-
}
5891-
case Intrinsic::amdgcn_interp_p2: {
5892-
SDValue ToM0 = DAG.getCopyToReg(DAG.getEntryNode(), DL, AMDGPU::M0,
5893-
Op.getOperand(5), SDValue());
5894-
return DAG.getNode(AMDGPUISD::INTERP_P2, DL, MVT::f32, Op.getOperand(1),
5895-
Op.getOperand(2), Op.getOperand(3), Op.getOperand(4),
5896-
ToM0.getValue(1));
5897-
}
58985879
case Intrinsic::amdgcn_interp_p1_f16: {
58995880
SDValue ToM0 = DAG.getCopyToReg(DAG.getEntryNode(), DL, AMDGPU::M0,
59005881
Op.getOperand(5), SDValue());
5901-
59025882
if (getSubtarget()->getLDSBankCount() == 16) {
59035883
// 16 bank LDS
5904-
SDValue S = DAG.getNode(AMDGPUISD::INTERP_MOV, DL, MVT::f32,
5905-
DAG.getConstant(2, DL, MVT::i32), // P0
5906-
Op.getOperand(2), // Attrchan
5907-
Op.getOperand(3), // Attr
5908-
ToM0.getValue(1));
5884+
5885+
// FIXME: This implicitly will insert a second CopyToReg to M0.
5886+
SDValue S = DAG.getNode(
5887+
ISD::INTRINSIC_WO_CHAIN, DL, MVT::f32,
5888+
DAG.getTargetConstant(Intrinsic::amdgcn_interp_mov, DL, MVT::i32),
5889+
DAG.getConstant(2, DL, MVT::i32), // P0
5890+
Op.getOperand(2), // Attrchan
5891+
Op.getOperand(3), // Attr
5892+
Op.getOperand(5)); // m0
5893+
59095894
SDValue Ops[] = {
59105895
Op.getOperand(1), // Src0
59115896
Op.getOperand(2), // Attrchan
@@ -10895,12 +10880,6 @@ bool SITargetLowering::isSDNodeSourceOfDivergence(const SDNode * N,
1089510880
case ISD::INTRINSIC_W_CHAIN:
1089610881
return AMDGPU::isIntrinsicSourceOfDivergence(
1089710882
cast<ConstantSDNode>(N->getOperand(1))->getZExtValue());
10898-
// In some cases intrinsics that are a source of divergence have been
10899-
// lowered to AMDGPUISD so we also need to check those too.
10900-
case AMDGPUISD::INTERP_MOV:
10901-
case AMDGPUISD::INTERP_P1:
10902-
case AMDGPUISD::INTERP_P2:
10903-
return true;
1090410883
}
1090510884
return false;
1090610885
}

‎llvm/lib/Target/AMDGPU/SIInstructions.td‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -43,8 +43,8 @@ multiclass V_INTERP_P1_F32_m : VINTRP_m <
4343
(outs VINTRPDst:$vdst),
4444
(ins VGPR_32:$vsrc, Attr:$attr, AttrChan:$attrchan),
4545
"v_interp_p1_f32$vdst, $vsrc, $attr$attrchan",
46-
[(set f32:$vdst, (AMDGPUinterp_p1 f32:$vsrc, (i32 timm:$attrchan),
47-
(i32 timm:$attr)))]
46+
[(set f32:$vdst, (int_amdgcn_interp_p1 f32:$vsrc,
47+
(i32 timm:$attrchan), (i32 timm:$attr), M0))]
4848
>;
4949

5050
let OtherPredicates = [has32BankLDS] in {
@@ -66,8 +66,8 @@ defm V_INTERP_P2_F32 : VINTRP_m <
6666
(outs VINTRPDst:$vdst),
6767
(ins VGPR_32:$src0, VGPR_32:$vsrc, Attr:$attr, AttrChan:$attrchan),
6868
"v_interp_p2_f32$vdst, $vsrc, $attr$attrchan",
69-
[(set f32:$vdst, (AMDGPUinterp_p2 f32:$src0, f32:$vsrc, (i32 timm:$attrchan),
70-
(i32 timm:$attr)))]>;
69+
[(set f32:$vdst, (int_amdgcn_interp_p2 f32:$src0, f32:$vsrc,
70+
(i32 timm:$attrchan), (i32 timm:$attr), M0))]>;
7171

7272
} // End DisableEncoding = "$src0", Constraints = "$src0 = $vdst"
7373

@@ -76,8 +76,8 @@ defm V_INTERP_MOV_F32 : VINTRP_m <
7676
(outs VINTRPDst:$vdst),
7777
(ins InterpSlot:$vsrc, Attr:$attr, AttrChan:$attrchan),
7878
"v_interp_mov_f32$vdst, $vsrc, $attr$attrchan",
79-
[(set f32:$vdst, (AMDGPUinterp_mov (i32 imm:$vsrc), (i32 timm:$attrchan),
80-
(i32 timm:$attr)))]>;
79+
[(set f32:$vdst, (int_amdgcn_interp_mov (i32 imm:$vsrc),
80+
(i32 timm:$attrchan), (i32 timm:$attr), M0))]>;
8181

8282
} // End Uses = [M0, EXEC]
8383

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