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[mips] Fix JmpLink to texternalsym and tglobaladdr on mcroMIPS R6
There is not match for the `MipsJmpLink texternalsym` and `MipsJmpLink tglobaladdr` patterns for microMIPS R6. As a result LLVM incorrectly selects the `JALRC16` compact 2-byte instruction which takes a target instruction address from a register only and assign `R_MIPS_32` relocation for this instruction. This relocation completely overwrites `JALRC16` and nearby instructions. This patch adds missed matching patterns, selects `BALC` instruction and assign a correct `R_MICROMIPS_PC26_S1` relocation. Differential Revision: https://reviews.llvm.org/D64552 llvm-svn: 365870
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6 files changed

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‎llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1774,6 +1774,19 @@ let AddedComplexity = 41 in {
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def : StoreRegImmPat<SDC1_D64_MMR6, f64>, FGR_64, ISA_MICROMIPS32R6;
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}
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let isCall=1, hasDelaySlot=0, isCTI=1, Defs = [RA] in {
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class JumpLinkMMR6<Instruction JumpInst, DAGOperand Opnd> :
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PseudoSE<(outs), (ins calltarget:$target), [], II_JAL>,
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PseudoInstExpansion<(JumpInst Opnd:$target)>;
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}
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def JAL_MMR6 : JumpLinkMMR6<BALC_MMR6, brtarget26_mm>, ISA_MICROMIPS32R6;
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def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
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(JAL_MMR6 texternalsym:$dst)>, ISA_MICROMIPS32R6;
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def : MipsPat<(MipsJmpLink (iPTR tglobaladdr:$dst)),
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(JAL_MMR6 tglobaladdr:$dst)>, ISA_MICROMIPS32R6;
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def TAILCALL_MMR6 : TailCall<BC_MMR6, brtarget26_mm>, ISA_MICROMIPS32R6;
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def TAILCALLREG_MMR6 : TailCallReg<JRC16_MM, GPR32Opnd>, ISA_MICROMIPS32R6;

‎llvm/lib/Target/Mips/MipsScheduleGeneric.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -384,7 +384,7 @@ def : InstRW<[GenericWriteJump], (instrs BC16_MMR6, BC1EQZC_MMR6, BC1NEZC_MMR6,
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BGTZC_MMR6, BLEZC_MMR6, BLTC_MMR6,
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BLTUC_MMR6, BLTZC_MMR6, BNEC_MMR6,
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BNEZC16_MMR6, BNEZC_MMR6, BNVC_MMR6,
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BOVC_MMR6, DERET_MMR6, ERETNC_MMR6,
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BOVC_MMR6, DERET_MMR6, ERETNC_MMR6, JAL_MMR6,
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ERET_MMR6, JIC_MMR6, JRADDIUSP, JRC16_MM,
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JRC16_MMR6, JRCADDIUSP_MMR6, SIGRIE_MMR6,
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B_MMR6_Pseudo, PseudoIndirectBranch_MMR6)>;

‎llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -208,7 +208,7 @@ define i32 @test1(float %t) {
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; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR6-SF-NEXT: # <MCOperand Imm:20>>
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; MMR6-SF-NEXT: .cfi_offset 31, -4
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; MMR6-SF-NEXT: jalr __fixsfsi # <MCInst #{{[0-9]+}} JALRC16_MMR6
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; MMR6-SF-NEXT: balc __fixsfsi # <MCInst #{{[0-9]+}} BALC_MMR6
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; MMR6-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>>
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; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
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; MMR6-SF-NEXT: # <MCInst #{{[0-9]+}} LW
@@ -399,7 +399,7 @@ define i32 @test2(double %t) {
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; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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; MMR6-SF-NEXT: # <MCOperand Imm:20>>
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; MMR6-SF-NEXT: .cfi_offset 31, -4
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; MMR6-SF-NEXT: jalr __fixdfsi # <MCInst #{{[0-9]+}} JALRC16_MMR6
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; MMR6-SF-NEXT: balc __fixdfsi # <MCInst #{{[0-9]+}} BALC_MMR6
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; MMR6-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>>
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; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
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; MMR6-SF-NEXT: # <MCInst #{{[0-9]+}} LW

‎llvm/test/CodeGen/Mips/micromips-delay-slot.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,5 +18,5 @@ declare i32 @bar(i32 signext) #1
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; CHECK: jals
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; CHECK-NEXT: sll16
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; CHECK-MMR6: jal
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; CHECK-MMR6: balc
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; CHECK-MMR6-NOT: sll16

‎llvm/test/CodeGen/Mips/micromips-target-external-symbol-reloc.ll‎

Lines changed: 13 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,23 @@
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; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips -stop-after=finalize-isel < %s | FileCheck %s
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; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips \
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; RUN: -stop-after=finalize-isel < %s | FileCheck --check-prefix=MM2 %s
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; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r6 -mattr=+micromips \
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; RUN: -stop-after=finalize-isel < %s | FileCheck --check-prefix=MM6 %s
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; CHECK: JAL_MM
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; CHECK-NOT: JALR16_MM
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; MM2: JAL_MM @bar
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; MM2: JAL_MM &memset
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; MM2-NOT: JALR16_MM
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; MM6: JAL_MMR6 @bar
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; MM6: JAL_MMR6 &memset
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; MM6-NOT: JALRC16_MMR6
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define dso_local void @foo(i32* nocapture %ar) local_unnamed_addr {
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entry:
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call void @bar()
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%0 = bitcast i32* %ar to i8*
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tail call void @llvm.memset.p0i8.i32(i8* align 4 %0, i8 0, i32 100, i1 false)
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ret void
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}
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declare void @llvm.memset.p0i8.i32(i8* nocapture writeonly, i8, i32, i1)
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declare void @bar()

‎llvm/test/CodeGen/Mips/tailcall/tailcall.ll‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,7 @@ entry:
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; PIC32MM: jalr $25
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; PIC32R6: jalr $25
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; STATIC32: jal
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; STATIC32MMR6: jal
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; STATIC32MMR6: balc
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; N64: jalr $25
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; N64R6: jalr $25
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; PIC16: jalrc
@@ -65,7 +65,7 @@ entry:
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; PIC32MM: jalr $25
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; PIC32R6: jalr $25
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; STATIC32: jal
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; STATIC32MMR6: jal
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; STATIC32MMR6: balc
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; N64: jalr $25
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; N64R6: jalr $25
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; PIC16: jalrc
@@ -83,7 +83,7 @@ entry:
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; PIC32R6: jalr $25
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; PIC32MM: jalr $25
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; STATIC32: jal
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; STATIC32MMR6: jal
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; STATIC32MMR6: balc
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; N64: jalr $25
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; N64R6: jalr $25
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; PIC16: jalrc
@@ -179,7 +179,7 @@ entry:
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; PIC32R6: jalr $25
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; PIC32MM: jalr $25
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; STATIC32: jal
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; STATIC32MMR6: jal
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; STATIC32MMR6: balc
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; PIC64: jalr $25
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; STATIC64: jal
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; PIC16: jalrc
@@ -217,7 +217,7 @@ entry:
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; PIC32R6: jalrc $25
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; PIC32MM: jalr $25
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; STATIC32: jal
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; STATIC32MMR6: jal
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; STATIC32MMR6: balc
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; STATIC64: jal
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; PIC64: jalr $25
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; PIC64R6: jalrc $25
@@ -236,7 +236,7 @@ entry:
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; PIC32R6: jalr $25
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; PIC32MM: jalr $25
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; STATIC32: jal
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; STATIC32MMR6: jal
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; STATIC32MMR6: balc
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; STATIC64: jal
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; PIC64: jalr $25
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; PIC64R6: jalr $25
@@ -255,7 +255,7 @@ entry:
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; PIC32R6: jalrc $25
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; PIC32MM: jalr $25
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; STATIC32: jal
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; STATIC32MMR6: jal
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; STATIC32MMR6: balc
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; STATIC64: jal
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; PIC64: jalr $25
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; PIC64R6: jalrc $25
@@ -276,7 +276,7 @@ entry:
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; PIC32R6: jalrc $25
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; PIC32MM: jalr $25
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; STATIC32: jal
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; STATIC32MMR6: jal
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; STATIC32MMR6: balc
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; STATIC64: jal
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; PIC64: jalr $25
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; PIC64R6: jalrc $25
@@ -297,7 +297,7 @@ entry:
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; PIC32R6: jalr $25
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; PIC32MM: jalr $25
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; STATIC32: jal
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; STATIC32MMR6: jal
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; STATIC32MMR6: balc
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; STATIC64: jal
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; PIC64R6: jalr $25
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; PIC64: jalr $25

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