Skip to content

Commit ec3ee1e

Browse files
s-barannikovs-barannikov
committed
[AArch64] Remove post-decoding instruction mutations
These instructions can now be fully decoded automatically.
1 parent 772f655 commit ec3ee1e

File tree

6 files changed

+102
-47
lines changed

6 files changed

+102
-47
lines changed

‎llvm/lib/Target/AArch64/AArch64InstrFormats.td‎

Lines changed: 17 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1561,13 +1561,11 @@ def VectorIndexHOperand : AsmVectorIndex<0, 7>;
15611561
def VectorIndexSOperand : AsmVectorIndex<0, 3>;
15621562
def VectorIndexDOperand : AsmVectorIndex<0, 1>;
15631563

1564-
let OperandNamespace = "AArch64" in {
1565-
let OperandType = "OPERAND_IMPLICIT_IMM_0" in {
1566-
defm VectorIndex0 : VectorIndex<i64, VectorIndex0Operand,
1567-
[{ return ((uint64_t)Imm) == 0; }]>;
1568-
defm VectorIndex032b : VectorIndex<i32, VectorIndex0Operand,
1569-
[{ return ((uint32_t)Imm) == 0; }]>;
1570-
}
1564+
let DecoderMethod = "DecodeZeroImm" in {
1565+
defm VectorIndex0 : VectorIndex<i64, VectorIndex0Operand,
1566+
[{ return ((uint64_t)Imm) == 0; }]>;
1567+
defm VectorIndex032b : VectorIndex<i32, VectorIndex0Operand,
1568+
[{ return ((uint32_t)Imm) == 0; }]>;
15711569
}
15721570
defm VectorIndex1 : VectorIndex<i64, VectorIndex1Operand,
15731571
[{ return ((uint64_t)Imm) == 1; }]>;
@@ -1617,9 +1615,8 @@ def sme_elm_idx0_0 : Operand<i32>, TImmLeaf<i32, [{
16171615
return ((uint32_t)Imm) == 0;
16181616
}]> {
16191617
let ParserMatchClass = Imm0_0Operand;
1618+
let DecoderMethod = "DecodeZeroImm";
16201619
let PrintMethod = "printMatrixIndex";
1621-
let OperandNamespace = "AArch64";
1622-
let OperandType = "OPERAND_IMPLICIT_IMM_0";
16231620
}
16241621
def sme_elm_idx0_1 : Operand<i32>, TImmLeaf<i32, [{
16251622
return ((uint32_t)Imm) <= 1;
@@ -1679,18 +1676,16 @@ def UImm3s2RangeOperand : UImmScaledMemoryIndexedRange<3, 2, 1>;
16791676

16801677
def uimm0s2range : Operand<i64>, ImmLeaf<i64,
16811678
[{ return Imm == 0; }], UImmS1XForm> {
1679+
let DecoderMethod = "DecodeZeroImm";
16821680
let PrintMethod = "printImmRangeScale<2, 1>";
16831681
let ParserMatchClass = UImm0s2RangeOperand;
1684-
let OperandNamespace = "AArch64";
1685-
let OperandType = "OPERAND_IMPLICIT_IMM_0";
16861682
}
16871683

16881684
def uimm0s4range : Operand<i64>, ImmLeaf<i64,
16891685
[{ return Imm == 0; }], UImmS1XForm> {
1686+
let DecoderMethod = "DecodeZeroImm";
16901687
let PrintMethod = "printImmRangeScale<4, 3>";
16911688
let ParserMatchClass = UImm0s4RangeOperand;
1692-
let OperandNamespace = "AArch64";
1693-
let OperandType = "OPERAND_IMPLICIT_IMM_0";
16941689
}
16951690

16961691
def uimm1s2range : Operand<i64>, ImmLeaf<i64,
@@ -8220,18 +8215,23 @@ multiclass SMov {
82208215
// streaming mode.
82218216
let Predicates = [HasNEONandIsStreamingSafe] in {
82228217
def vi8to32_idx0 : SIMDSMov<0, ".b", GPR32, VectorIndex0> {
8218+
bits<0> idx;
82238219
let Inst{20-16} = 0b00001;
82248220
}
82258221
def vi8to64_idx0 : SIMDSMov<1, ".b", GPR64, VectorIndex0> {
8222+
bits<0> idx;
82268223
let Inst{20-16} = 0b00001;
82278224
}
82288225
def vi16to32_idx0 : SIMDSMov<0, ".h", GPR32, VectorIndex0> {
8226+
bits<0> idx;
82298227
let Inst{20-16} = 0b00010;
82308228
}
82318229
def vi16to64_idx0 : SIMDSMov<1, ".h", GPR64, VectorIndex0> {
8230+
bits<0> idx;
82328231
let Inst{20-16} = 0b00010;
82338232
}
82348233
def vi32to64_idx0 : SIMDSMov<1, ".s", GPR64, VectorIndex0> {
8234+
bits<0> idx;
82358235
let Inst{20-16} = 0b00100;
82368236
}
82378237
}
@@ -8267,15 +8267,19 @@ multiclass UMov {
82678267
// streaming mode.
82688268
let Predicates = [HasNEONandIsStreamingSafe] in {
82698269
def vi8_idx0 : SIMDUMov<0, ".b", v16i8, GPR32, VectorIndex0> {
8270+
bits<0> idx;
82708271
let Inst{20-16} = 0b00001;
82718272
}
82728273
def vi16_idx0 : SIMDUMov<0, ".h", v8i16, GPR32, VectorIndex0> {
8274+
bits<0> idx;
82738275
let Inst{20-16} = 0b00010;
82748276
}
82758277
def vi32_idx0 : SIMDUMov<0, ".s", v4i32, GPR32, VectorIndex0> {
8278+
bits<0> idx;
82768279
let Inst{20-16} = 0b00100;
82778280
}
82788281
def vi64_idx0 : SIMDUMov<1, ".d", v2i64, GPR64, VectorIndex0> {
8282+
bits<0> idx;
82798283
let Inst{20-16} = 0b01000;
82808284
}
82818285
def : SIMDMovAlias<"mov", ".s",

‎llvm/lib/Target/AArch64/CMakeLists.txt‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,8 +7,7 @@ tablegen(LLVM AArch64GenAsmWriter.inc -gen-asm-writer)
77
tablegen(LLVM AArch64GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
88
tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv)
99
tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel)
10-
tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler
11-
-ignore-non-decodable-operands)
10+
tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler)
1211
tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel)
1312
tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)
1413
tablegen(LLVM AArch64GenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner

‎llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp‎

Lines changed: 22 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -130,6 +130,16 @@ DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
130130
return Success;
131131
}
132132

133+
static void DecodeMPRRegisterClass(MCInst &Inst,
134+
const MCDisassembler *Decoder) {
135+
Inst.addOperand(MCOperand::createReg(AArch64::ZA));
136+
}
137+
138+
static void DecodeZTRRegisterClass(MCInst &Inst,
139+
const MCDisassembler *Decoder) {
140+
Inst.addOperand(MCOperand::createReg(AArch64::ZT0));
141+
}
142+
133143
static const MCPhysReg MatrixZATileDecoderTable[5][16] = {
134144
{AArch64::ZAB0},
135145
{AArch64::ZAH0, AArch64::ZAH1},
@@ -141,10 +151,17 @@ static const MCPhysReg MatrixZATileDecoderTable[5][16] = {
141151
AArch64::ZAQ10, AArch64::ZAQ11, AArch64::ZAQ12, AArch64::ZAQ13,
142152
AArch64::ZAQ14, AArch64::ZAQ15}};
143153

154+
template <unsigned NumBitsForTile>
155+
static void DecodeMatrixTile(MCInst &Inst, const MCDisassembler *Decoder) {
156+
static_assert(NumBitsForTile == 0);
157+
Inst.addOperand(MCOperand::createReg(AArch64::ZAB0));
158+
}
159+
144160
template <unsigned NumBitsForTile>
145161
static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
146162
uint64_t Address,
147163
const MCDisassembler *Decoder) {
164+
static_assert(NumBitsForTile != 0);
148165
unsigned LastReg = (1 << NumBitsForTile) - 1;
149166
if (RegNo > LastReg)
150167
return Fail;
@@ -1422,6 +1439,10 @@ DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
14221439
return Success;
14231440
}
14241441

1442+
static void DecodeZeroImm(MCInst &Inst, const MCDisassembler *Decoder) {
1443+
Inst.addOperand(MCOperand::createImm(0));
1444+
}
1445+
14251446
template <int Bits>
14261447
static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
14271448
const MCDisassembler *Decoder) {
@@ -1570,6 +1591,7 @@ DecodeSMESpillFillInstruction(MCInst &Inst, uint32_t Bits, uint64_t Addr,
15701591
unsigned RnBits = fieldFromInstruction(Bits, 5, 5);
15711592
unsigned Imm4Bits = fieldFromInstruction(Bits, 0, 4);
15721593

1594+
DecodeMPRRegisterClass(Inst, Decoder);
15731595
DecodeSimpleRegisterClass<AArch64::MatrixIndexGPR32_12_15RegClassID, 0, 4>(
15741596
Inst, RvBits, Addr, Decoder);
15751597
Inst.addOperand(MCOperand::createImm(Imm4Bits));
@@ -1613,33 +1635,6 @@ DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
16131635
for (const auto *Table : Tables) {
16141636
DecodeStatus Result =
16151637
decodeInstruction(Table, MI, Insn, Address, this, STI);
1616-
1617-
const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
1618-
1619-
// For Scalable Matrix Extension (SME) instructions that have an implicit
1620-
// operand for the accumulator (ZA) or implicit immediate zero which isn't
1621-
// encoded, manually insert operand.
1622-
for (unsigned i = 0; i < Desc.getNumOperands(); i++) {
1623-
if (Desc.operands()[i].OperandType == MCOI::OPERAND_REGISTER) {
1624-
switch (Desc.operands()[i].RegClass) {
1625-
default:
1626-
break;
1627-
case AArch64::MPRRegClassID:
1628-
MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZA));
1629-
break;
1630-
case AArch64::MPR8RegClassID:
1631-
MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZAB0));
1632-
break;
1633-
case AArch64::ZTRRegClassID:
1634-
MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZT0));
1635-
break;
1636-
}
1637-
} else if (Desc.operands()[i].OperandType ==
1638-
AArch64::OPERAND_IMPLICIT_IMM_0) {
1639-
MI.insert(MI.begin() + i, MCOperand::createImm(0));
1640-
}
1641-
}
1642-
16431638
if (Result != MCDisassembler::Fail)
16441639
return Result;
16451640
}

‎llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -69,8 +69,7 @@ bool isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII);
6969

7070
namespace AArch64 {
7171
enum OperandType {
72-
OPERAND_IMPLICIT_IMM_0 = MCOI::OPERAND_FIRST_TARGET,
73-
OPERAND_SHIFT_MSL,
72+
OPERAND_SHIFT_MSL = MCOI::OPERAND_FIRST_TARGET,
7473
};
7574
} // namespace AArch64
7675

0 commit comments

Comments
 (0)