@@ -4756,31 +4756,19 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
47564756 SDValue N1 = Node->getOperand (1 );
47574757
47584758 unsigned Opc, MOpc;
4759- bool isSigned = Opcode == ISD::SMUL_LOHI;
4760- if (!isSigned) {
4761- switch (NVT.SimpleTy ) {
4762- default : llvm_unreachable (" Unsupported VT!" );
4763- case MVT::i32 : Opc = X86::MUL32r; MOpc = X86::MUL32m; break ;
4764- case MVT::i64 : Opc = X86::MUL64r; MOpc = X86::MUL64m; break ;
4765- }
4766- } else {
4767- switch (NVT.SimpleTy ) {
4768- default : llvm_unreachable (" Unsupported VT!" );
4769- case MVT::i32 : Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break ;
4770- case MVT::i64 : Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break ;
4771- }
4772- }
4773-
4774- unsigned SrcReg, LoReg, HiReg;
4775- switch (Opc) {
4776- default : llvm_unreachable (" Unknown MUL opcode!" );
4777- case X86::IMUL32r:
4778- case X86::MUL32r:
4779- SrcReg = LoReg = X86::EAX; HiReg = X86::EDX;
4759+ unsigned LoReg, HiReg;
4760+ bool IsSigned = Opcode == ISD::SMUL_LOHI;
4761+ switch (NVT.SimpleTy ) {
4762+ default : llvm_unreachable (" Unsupported VT!" );
4763+ case MVT::i32 :
4764+ Opc = IsSigned ? X86::IMUL32r : X86::MUL32r;
4765+ MOpc = IsSigned ? X86::IMUL32m : X86::MUL32m;
4766+ LoReg = X86::EAX; HiReg = X86::EDX;
47804767 break ;
4781- case X86::IMUL64r:
4782- case X86::MUL64r:
4783- SrcReg = LoReg = X86::RAX; HiReg = X86::RDX;
4768+ case MVT::i64 :
4769+ Opc = IsSigned ? X86::IMUL64r : X86::MUL64r;
4770+ MOpc = IsSigned ? X86::IMUL64m : X86::MUL64m;
4771+ LoReg = X86::RAX; HiReg = X86::RDX;
47844772 break ;
47854773 }
47864774
@@ -4793,7 +4781,7 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
47934781 std::swap (N0, N1);
47944782 }
47954783
4796- SDValue InFlag = CurDAG->getCopyToReg (CurDAG->getEntryNode (), dl, SrcReg ,
4784+ SDValue InFlag = CurDAG->getCopyToReg (CurDAG->getEntryNode (), dl, LoReg ,
47974785 N0, SDValue ()).getValue (1 );
47984786 if (foldedLoad) {
47994787 SDValue Chain;
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