Undo renames + put back std::optional

lukel97 · lukel97 · commit e54c16236ce5 · 2025-01-28T19:58:42.000+08:00
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -4235,8 +4235,6 @@ unsigned RISCV::getDestLog2EEW(const MCInstrDesc &Desc, unsigned Log2SEW) {
 
 /// Given two VL operands, do we know that LHS <= RHS?
 bool RISCV::isVLKnownLE(const MachineOperand &LHS, const MachineOperand &RHS) {
-  if (LHS.isImm() && LHS.getImm() == 0)
-    return true;
   if (LHS.isReg() && RHS.isReg() && LHS.getReg().isVirtual() &&
       LHS.getReg() == RHS.getReg())
     return true;
diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -51,11 +51,10 @@ class RISCVVLOptimizer : public MachineFunctionPass {
   StringRef getPassName() const override { return PASS_NAME; }
 
 private:
-  MachineOperand getMinimumVLForUser(MachineOperand &UserOp);
-  /// Computes the minimum demanded VL of \p MI, i.e. the minimum VL that's used
-  /// by its users downstream.
-  /// Returns 0 if MI has no users.
-  MachineOperand computeDemandedVL(const MachineInstr &MI);
+  std::optional<MachineOperand> getMinimumVLForUser(MachineOperand &UserOp);
+  /// Returns the largest common VL MachineOperand that may be used to optimize
+  /// MI. Returns std::nullopt if it failed to find a suitable VL.
+  std::optional<MachineOperand> checkUsers(MachineInstr &MI);
   bool tryReduceVL(MachineInstr &MI);
   bool isCandidate(const MachineInstr &MI) const;
 
@@ -1179,14 +1178,15 @@ bool RISCVVLOptimizer::isCandidate(const MachineInstr &MI) const {
   return true;
 }
 
-MachineOperand RISCVVLOptimizer::getMinimumVLForUser(MachineOperand &UserOp) {
+std::optional<MachineOperand>
+RISCVVLOptimizer::getMinimumVLForUser(MachineOperand &UserOp) {
   const MachineInstr &UserMI = *UserOp.getParent();
   const MCInstrDesc &Desc = UserMI.getDesc();
 
   if (!RISCVII::hasVLOp(Desc.TSFlags) || !RISCVII::hasSEWOp(Desc.TSFlags)) {
     LLVM_DEBUG(dbgs() << "    Abort due to lack of VL, assume that"
                          " use VLMAX\n");
-    return MachineOperand::CreateImm(RISCV::VLMaxSentinel);
+    return std::nullopt;
   }
 
   // Instructions like reductions may use a vector register as a scalar
@@ -1223,40 +1223,39 @@ MachineOperand RISCVVLOptimizer::getMinimumVLForUser(MachineOperand &UserOp) {
   return VLOp;
 }
 
-MachineOperand RISCVVLOptimizer::computeDemandedVL(const MachineInstr &MI) {
-  const MachineOperand &VLMAX = MachineOperand::CreateImm(RISCV::VLMaxSentinel);
-  MachineOperand DemandedVL = MachineOperand::CreateImm(0);
-
+std::optional<MachineOperand> RISCVVLOptimizer::checkUsers(MachineInstr &MI) {
+  std::optional<MachineOperand> CommonVL;
   for (auto &UserOp : MRI->use_operands(MI.getOperand(0).getReg())) {
     const MachineInstr &UserMI = *UserOp.getParent();
     LLVM_DEBUG(dbgs() << "  Checking user: " << UserMI << "\n");
     if (mayReadPastVL(UserMI)) {
       LLVM_DEBUG(dbgs() << "    Abort because used by unsafe instruction\n");
-      return VLMAX;
+      return std::nullopt;
     }
 
     // If used as a passthru, elements past VL will be read.
     if (UserOp.isTied()) {
       LLVM_DEBUG(dbgs() << "    Abort because user used as tied operand\n");
-      return VLMAX;
+      return std::nullopt;
     }
 
-    const MachineOperand &VLOp = getMinimumVLForUser(UserOp);
-
-    // The minimum demanded VL is the largest VL read amongst all the users. If
-    // we cannot determine this statically, then we cannot optimize the VL.
-    if (RISCV::isVLKnownLE(DemandedVL, VLOp)) {
-      DemandedVL = VLOp;
-      LLVM_DEBUG(dbgs() << "    Demanded VL is: " << VLOp << "\n");
-    } else if (!RISCV::isVLKnownLE(VLOp, DemandedVL)) {
-      LLVM_DEBUG(
-          dbgs() << "    Abort because cannot determine the demanded VL\n");
-      return VLMAX;
+    auto VLOp = getMinimumVLForUser(UserOp);
+    if (!VLOp)
+      return std::nullopt;
+
+    // Use the largest VL among all the users. If we cannot determine this
+    // statically, then we cannot optimize the VL.
+    if (!CommonVL || RISCV::isVLKnownLE(*CommonVL, *VLOp)) {
+      CommonVL = *VLOp;
+      LLVM_DEBUG(dbgs() << "    User VL is: " << VLOp << "\n");
+    } else if (!RISCV::isVLKnownLE(*VLOp, *CommonVL)) {
+      LLVM_DEBUG(dbgs() << "    Abort because cannot determine a common VL\n");
+      return std::nullopt;
     }
 
     if (!RISCVII::hasSEWOp(UserMI.getDesc().TSFlags)) {
       LLVM_DEBUG(dbgs() << "    Abort due to lack of SEW operand\n");
-      return VLMAX;
+      return std::nullopt;
     }
 
     std::optional<OperandInfo> ConsumerInfo = getOperandInfo(UserOp, MRI);
@@ -1266,7 +1265,7 @@ MachineOperand RISCVVLOptimizer::computeDemandedVL(const MachineInstr &MI) {
       LLVM_DEBUG(dbgs() << "    Abort due to unknown operand information.\n");
       LLVM_DEBUG(dbgs() << "      ConsumerInfo is: " << ConsumerInfo << "\n");
       LLVM_DEBUG(dbgs() << "      ProducerInfo is: " << ProducerInfo << "\n");
-      return VLMAX;
+      return std::nullopt;
     }
 
     // If the operand is used as a scalar operand, then the EEW must be
@@ -1281,52 +1280,53 @@ MachineOperand RISCVVLOptimizer::computeDemandedVL(const MachineInstr &MI) {
           << "    Abort due to incompatible information for EMUL or EEW.\n");
       LLVM_DEBUG(dbgs() << "      ConsumerInfo is: " << ConsumerInfo << "\n");
       LLVM_DEBUG(dbgs() << "      ProducerInfo is: " << ProducerInfo << "\n");
-      return VLMAX;
+      return std::nullopt;
     }
   }
 
-  return DemandedVL;
+  return CommonVL;
 }
 
 bool RISCVVLOptimizer::tryReduceVL(MachineInstr &MI) {
   LLVM_DEBUG(dbgs() << "Trying to reduce VL for " << MI << "\n");
 
-  const MachineOperand &DemandedVL = DemandedVLs.at(&MI);
+  if (!DemandedVLs.contains(&MI))
+    return false;
+  auto CommonVL = std::make_optional(DemandedVLs.at(&MI));
 
-  assert((DemandedVL.isImm() || DemandedVL.getReg().isVirtual()) &&
+  assert((CommonVL->isImm() || CommonVL->getReg().isVirtual()) &&
          "Expected VL to be an Imm or virtual Reg");
 
   unsigned VLOpNum = RISCVII::getVLOpNum(MI.getDesc());
   MachineOperand &VLOp = MI.getOperand(VLOpNum);
 
-  if (!RISCV::isVLKnownLE(DemandedVL, VLOp)) {
-    LLVM_DEBUG(dbgs() << "    Abort due to DemandedVL not <= VLOp.\n");
+  if (!RISCV::isVLKnownLE(*CommonVL, VLOp)) {
+    LLVM_DEBUG(dbgs() << "    Abort due to CommonVL not <= VLOp.\n");
     return false;
   }
 
-  if (DemandedVL.isIdenticalTo(VLOp)) {
+  if (CommonVL->isIdenticalTo(VLOp)) {
     LLVM_DEBUG(
-        dbgs()
-        << "    Abort due to DemandedVL == VLOp, no point in reducing.\n");
+        dbgs() << "    Abort due to CommonVL == VLOp, no point in reducing.\n");
     return false;
   }
 
-  if (DemandedVL.isImm()) {
+  if (CommonVL->isImm()) {
     LLVM_DEBUG(dbgs() << "  Reduce VL from " << VLOp << " to "
-                      << DemandedVL.getImm() << " for " << MI << "\n");
-    VLOp.ChangeToImmediate(DemandedVL.getImm());
+                      << CommonVL->getImm() << " for " << MI << "\n");
+    VLOp.ChangeToImmediate(CommonVL->getImm());
     return true;
   }
-  const MachineInstr *VLMI = MRI->getVRegDef(DemandedVL.getReg());
+  const MachineInstr *VLMI = MRI->getVRegDef(CommonVL->getReg());
   if (!MDT->dominates(VLMI, &MI))
     return false;
   LLVM_DEBUG(
       dbgs() << "  Reduce VL from " << VLOp << " to "
-             << printReg(DemandedVL.getReg(), MRI->getTargetRegisterInfo())
+             << printReg(CommonVL->getReg(), MRI->getTargetRegisterInfo())
              << " for " << MI << "\n");
 
   // All our checks passed. We can reduce VL.
-  VLOp.ChangeToRegister(DemandedVL.getReg(), false);
+  VLOp.ChangeToRegister(CommonVL->getReg(), false);
   return true;
 }
 
@@ -1351,10 +1351,11 @@ bool RISCVVLOptimizer::runOnMachineFunction(MachineFunction &MF) {
 
     // For each instruction that defines a vector, compute what VL its
     // downstream users demand.
-    for (const auto &MI : reverse(MBB)) {
+    for (MachineInstr &MI : reverse(MBB)) {
       if (!isCandidate(MI))
         continue;
-      DemandedVLs.insert({&MI, computeDemandedVL(MI)});
+      if (auto DemandedVL = checkUsers(MI))
+	DemandedVLs.insert({&MI, *DemandedVL});
     }
 
     // Then go through and see if we can reduce the VL of any instructions to
diff --git a/llvm/test/CodeGen/RISCV/rvv/vlopt-same-vl.ll b/llvm/test/CodeGen/RISCV/rvv/vlopt-same-vl.ll
@@ -5,22 +5,22 @@
 
 ; GitHub Issue #123862 provided a case where the riscv-vl-optimizer pass was
 ; very slow. It was found that that case benefited greatly from aborting due
-; to DemandedVL == VLOp. Adding the case provided in the issue would show up
+; to CommonVL == VLOp. Adding the case provided in the issue would show up
 ; as a long running test instead of a test failure. We would likley have a hard
 ; time figuring if that case had a regression. So instead, we check this output
 ; which was responsible for speeding it up. 
 
 define <vscale x 4 x i32> @same_vl_imm(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
-  ; CHECK: Demanded VL is: 4
-  ; CHECK: Abort due to DemandedVL == VLOp, no point in reducing.
+  ; CHECK: User VL is: 4
+  ; CHECK: Abort due to CommonVL == VLOp, no point in reducing.
   %v = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i64 4)
   %w = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %v, <vscale x 4 x i32> %a, i64 4)
   ret <vscale x 4 x i32> %w
 }
 
 define <vscale x 4 x i32> @same_vl_reg(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i64 %vl) {
-  ; CHECK: Demanded VL is: %3:gprnox0
-  ; CHECK: Abort due to DemandedVL == VLOp, no point in reducing.
+  ; CHECK: User VL is: %3:gprnox0
+  ; CHECK: Abort due to CommonVL == VLOp, no point in reducing.
   %v = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i64 %vl)
   %w = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %v, <vscale x 4 x i32> %a, i64 %vl)
   ret <vscale x 4 x i32> %w
