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[RISCV][MC] MC layer support for the experimental zalasr extension (#79911)
This PR implements experimental support for the RISC-V Atomic Load-Acquire and Store-Release Extension (Zalasr). It has been approved to be pursued as a fast track extension (https://lists.riscv.org/g/tech-unprivileged/topic/arc_architecture_review/101951698), but has not yet been approved by ARC or ratified. See https://github.com/mehnadnerd/riscv-zalasr for draft spec. --------- Co-authored-by: brs <[email protected]> Co-authored-by: Philip Reames <[email protected]>
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‎clang/test/Preprocessor/riscv-target-features.c‎

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@@ -144,6 +144,7 @@
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// CHECK-NOT: __riscv_zaamo {{.*$}}
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// CHECK-NOT: __riscv_zacas {{.*$}}
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// CHECK-NOT: __riscv_zalasr {{.*$}}
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// CHECK-NOT: __riscv_zalrsc {{.*$}}
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// CHECK-NOT: __riscv_zcmop {{.*$}}
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// CHECK-NOT: __riscv_zfbfmin {{.*$}}
@@ -1333,6 +1334,14 @@
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZACAS-EXT %s
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// CHECK-ZACAS-EXT: __riscv_zacas 1000000{{$}}
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// RUN: %clang --target=riscv32 -menable-experimental-extensions \
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// RUN: -march=rv32i_zalasr0p1 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZALASR-EXT %s
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// RUN: %clang --target=riscv64 -menable-experimental-extensions \
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// RUN: -march=rv64i_zalasr0p1 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZALASR-EXT %s
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// CHECK-ZALASR-EXT: __riscv_zalasr 1000{{$}}
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// RUN: %clang --target=riscv32 -menable-experimental-extensions \
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// RUN: -march=rv32i_zalrsc0p2 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZALRSC-EXT %s

‎llvm/docs/RISCVUsage.rst‎

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@@ -232,6 +232,9 @@ The primary goal of experimental support is to assist in the process of ratifica
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``experimental-zacas``
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LLVM implements the `1.0-rc1 draft specification <https://github.com/riscv/riscv-zacas/releases/tag/v1.0-rc1>`_.
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``experimental-zalasr``
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LLVM implements the `0.0.5 draft specification <https://github.com/mehnadnerd/riscv-zalasr>`_.
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``experimental-zfbfmin``, ``experimental-zvfbfmin``, ``experimental-zvfbfwma``
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LLVM implements assembler support for the `1.0.0-rc2 specification <https://github.com/riscv/riscv-bfloat16/releases/tag/v59042fc71c31a9bcb2f1957621c960ed36fac401>`_.
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‎llvm/lib/Support/RISCVISAInfo.cpp‎

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@@ -197,6 +197,7 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
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{"zaamo", {0, 2}},
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{"zabha", {1, 0}},
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{"zacas", {1, 0}},
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{"zalasr", {0, 1}},
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{"zalrsc", {0, 2}},
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{"zcmop", {0, 2}},

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

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@@ -192,6 +192,13 @@ def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">,
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"'Zacas' (Atomic Compare-And-Swap Instructions)">;
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def NoStdExtZacas : Predicate<"!Subtarget->hasStdExtZacas()">;
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def FeatureStdExtZalasr
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: SubtargetFeature<"experimental-zalasr", "HasStdExtZalasr", "true",
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"'Zalasr' (Load-Acquire and Store-Release Instructions)">;
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def HasStdExtZalasr : Predicate<"Subtarget->hasStdExtZalasr()">,
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AssemblerPredicate<(all_of FeatureStdExtZalasr),
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"'Zalasr' (Load-Acquire and Store-Release Instructions)">;
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def FeatureStdExtZalrsc
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: SubtargetFeature<"experimental-zalrsc", "HasStdExtZalrsc", "true",
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"'Zalrsc' (Load-Reserved/Store-Conditional)">;

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td‎

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@@ -2146,6 +2146,7 @@ include "RISCVInstrInfoM.td"
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// Atomic
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include "RISCVInstrInfoA.td"
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include "RISCVInstrInfoZa.td"
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include "RISCVInstrInfoZalasr.td"
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// Scalar FP
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include "RISCVInstrInfoF.td"

‎llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td‎

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//===-- RISCVInstrInfoZalasr.td ---------------------------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the RISC-V instructions from the Zalasr (Load-Acquire
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// and Store-Release) extension
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction class templates
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
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class LAQ_r<bit aq, bit rl, bits<3> funct3, string opcodestr>
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: RVInstRAtomic<0b00110, aq, rl, funct3, OPC_AMO,
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(outs GPR:$rd), (ins GPRMemZeroOffset:$rs1),
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opcodestr, "$rd, $rs1"> {
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let rs2 = 0;
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}
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let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
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class SRL_r<bit aq, bit rl, bits<3> funct3, string opcodestr>
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: RVInstRAtomic<0b00111, aq, rl, funct3, OPC_AMO,
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(outs ), (ins GPRMemZeroOffset:$rs1, GPR:$rs2),
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opcodestr, "$rs2, $rs1"> {
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let rd = 0;
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}
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multiclass LAQ_r_aq_rl<bits<3> funct3, string opcodestr> {
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def _AQ : LAQ_r<1, 0, funct3, opcodestr # ".aq">;
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def _AQ_RL : LAQ_r<1, 1, funct3, opcodestr # ".aqrl">;
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}
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multiclass SRL_r_aq_rl<bits<3> funct3, string opcodestr> {
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def _RL : SRL_r<0, 1, funct3, opcodestr # ".rl">;
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def _AQ_RL : SRL_r<1, 1, funct3, opcodestr # ".aqrl">;
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}
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtZalasr] in {
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defm LB : LAQ_r_aq_rl<0b000, "lb">;
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defm LH : LAQ_r_aq_rl<0b001, "lh">;
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defm LW : LAQ_r_aq_rl<0b010, "lw">;
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defm SB : SRL_r_aq_rl<0b000, "sb">;
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defm SH : SRL_r_aq_rl<0b001, "sh">;
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defm SW : SRL_r_aq_rl<0b010, "sw">;
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} // Predicates = [HasStdExtZalasr]
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let Predicates = [HasStdExtZalasr, IsRV64] in {
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defm LD : LAQ_r_aq_rl<0b011, "ld">;
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defm SD : SRL_r_aq_rl<0b011, "sd">;
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} // Predicates = [HasStdExtZalasr, IsRV64]

‎llvm/test/CodeGen/RISCV/attributes.ll‎

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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFWMA %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zaamo %s -o - | FileCheck --check-prefix=RV32ZAAMO %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zacas %s -o - | FileCheck --check-prefix=RV32ZACAS %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zalasr %s -o - | FileCheck --check-prefix=RV32ZALASR %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zalrsc %s -o - | FileCheck --check-prefix=RV32ZALRSC %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV32ZICFILP %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zabha %s -o - | FileCheck --check-prefix=RV32ZABHA %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFWMA %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zaamo %s -o - | FileCheck --check-prefix=RV64ZAAMO %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zacas %s -o - | FileCheck --check-prefix=RV64ZACAS %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zalasr %s -o - | FileCheck --check-prefix=RV64ZALASR %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zalrsc %s -o - | FileCheck --check-prefix=RV64ZALRSC %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV64ZICFILP %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zabha %s -o - | FileCheck --check-prefix=RV64ZABHA %s
@@ -300,6 +302,7 @@
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; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
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; RV32ZAAMO: .attribute 5, "rv32i2p1_zaamo0p2"
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; RV32ZACAS: .attribute 5, "rv32i2p1_a2p1_zacas1p0"
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; RV32ZALASR: .attribute 5, "rv32i2p1_zalasr0p1"
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; RV32ZALRSC: .attribute 5, "rv32i2p1_zalrsc0p2"
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; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp0p4"
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; RV32ZABHA: .attribute 5, "rv32i2p1_a2p1_zabha1p0"
@@ -404,6 +407,7 @@
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; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
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; RV64ZAAMO: .attribute 5, "rv64i2p1_zaamo0p2"
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; RV64ZACAS: .attribute 5, "rv64i2p1_a2p1_zacas1p0"
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; RV64ZALASR: .attribute 5, "rv64i2p1_zalasr0p1"
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; RV64ZALRSC: .attribute 5, "rv64i2p1_zalrsc0p2"
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; RV64ZICFILP: .attribute 5, "rv64i2p1_zicfilp0p4"
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; RV64ZABHA: .attribute 5, "rv64i2p1_a2p1_zabha1p0"

‎llvm/test/MC/RISCV/attribute-arch.s‎

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.attribute arch, "rv32izacas1p0"
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# CHECK: attribute 5, "rv32i2p1_a2p1_zacas1p0"
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.attribute arch, "rv32izalasr0p1"
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# CHECK: attribute 5, "rv32i2p1_zalasr0p1"
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.attribute arch, "rv32i_xcvalu"
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# CHECK: attribute 5, "rv32i2p1_xcvalu1p0"
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‎llvm/test/MC/RISCV/rv32zalasr-invalid.s‎

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# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zalasr < %s 2>&1 | FileCheck -check-prefixes=CHECK %s
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# CHECK: error: instruction requires the following: RV64I Base Instruction Set{{$}}
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ld.aq a1, (t0)
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# CHECK: error: instruction requires the following: RV64I Base Instruction Set{{$}}
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ld.aqrl a1, (t0)
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# CHECK: error: instruction requires the following: RV64I Base Instruction Set{{$}}
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sd.rl a1, (t0)
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# CHECK: error: instruction requires the following: RV64I Base Instruction Set{{$}}
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sd.aqrl a1, (t0)
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# CHECK: error: unrecognized instruction mnemonic
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lw. a1, (t0)
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# CHECK: error: unrecognized instruction mnemonic
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lw.rl t3, 0(t5)
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# CHECK: error: unrecognized instruction mnemonic
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lh.rlaq t4, (t6)
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# CHECK: error: unrecognized instruction mnemonic
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sb. a1, (t0)
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# CHECK: error: unrecognized instruction mnemonic
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sh.aq t3, 0(t5)
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# CHECK: error: unrecognized instruction mnemonic
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sh.rlaq t4, (t6)
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# CHECK: error: optional integer offset must be 0
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lw.aq zero, 1(a0)
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# CHECK: error: optional integer offset must be 0
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sw.rl t1, 2(s0)
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# CHECK: error: optional integer offset must be 0
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sb.aqrl sp, 3(s2)

‎llvm/test/MC/RISCV/rv32zalasr-valid.s‎

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# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zalasr -riscv-no-aliases -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
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# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zalasr < %s \
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# RUN: | llvm-objdump --mattr=+experimental-zalasr -M no-aliases -d -r - \
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# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
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# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zalasr -riscv-no-aliases -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
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# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zalasr < %s \
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# RUN: | llvm-objdump --mattr=+experimental-zalasr -M no-aliases -d -r - \
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# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
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#
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# RUN: not llvm-mc -triple riscv32 \
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# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
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# RUN: | FileCheck --check-prefixes=CHECK-NO-EXT %s
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# RUN: not llvm-mc -triple riscv64 \
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# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
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# RUN: | FileCheck --check-prefixes=CHECK-NO-EXT %s
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# CHECK-ASM-AND-OBJ: lb.aq t1, (a0)
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# CHECK-ASM: encoding: [0x2f,0x03,0x05,0x34]
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# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
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lb.aq t1, 0(a0)
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# CHECK-ASM-AND-OBJ: lh.aq t1, (a0)
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# CHECK-ASM: encoding: [0x2f,0x13,0x05,0x34]
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# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
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lh.aq t1, 0(a0)
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# CHECK-ASM-AND-OBJ: lw.aq t1, (a0)
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# CHECK-ASM: encoding: [0x2f,0x23,0x05,0x34]
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# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
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lw.aq t1, (a0)
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# CHECK-ASM-AND-OBJ: lb.aqrl t1, (a0)
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# CHECK-ASM: encoding: [0x2f,0x03,0x05,0x36]
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# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
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lb.aqrl t1, 0(a0)
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# CHECK-ASM-AND-OBJ: lh.aqrl t1, (a0)
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# CHECK-ASM: encoding: [0x2f,0x13,0x05,0x36]
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# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
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lh.aqrl t1, (a0)
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# CHECK-ASM-AND-OBJ: lw.aqrl t1, (a0)
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# CHECK-ASM: encoding: [0x2f,0x23,0x05,0x36]
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# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
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lw.aqrl t1, (a0)
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# CHECK-ASM-AND-OBJ: sb.rl t1, (a0)
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# CHECK-ASM: encoding: [0x2f,0x00,0x65,0x3a]
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# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
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sb.rl t1, (a0)
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# CHECK-ASM-AND-OBJ: sh.rl t1, (a0)
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# CHECK-ASM: encoding: [0x2f,0x10,0x65,0x3a]
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# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
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sh.rl t1, 0(a0)
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# CHECK-ASM-AND-OBJ: sw.rl t1, (a0)
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# CHECK-ASM: encoding: [0x2f,0x20,0x65,0x3a]
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# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
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sw.rl t1, (a0)
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# CHECK-ASM-AND-OBJ: sb.aqrl t1, (a0)
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# CHECK-ASM: encoding: [0x2f,0x00,0x65,0x3e]
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# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
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sb.aqrl t1, (a0)
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# CHECK-ASM-AND-OBJ: sh.aqrl t1, (a0)
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# CHECK-ASM: encoding: [0x2f,0x10,0x65,0x3e]
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# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
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sh.aqrl t1, 0(a0)
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# CHECK-ASM-AND-OBJ: sw.aqrl t1, (a0)
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# CHECK-ASM: encoding: [0x2f,0x20,0x65,0x3e]
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# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
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sw.aqrl t1, 0(a0)

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