add option to set max allowed instructins

Author: zhaoqi5

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

@@ -18,6 +18,7 @@
 #include "LoongArchSubtarget.h"
 #include "MCTargetDesc/LoongArchBaseInfo.h"
 #include "MCTargetDesc/LoongArchMCTargetDesc.h"
+#include "MCTargetDesc/LoongArchMatInt.h"
 #include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/ADT/StringExtras.h"
@@ -41,6 +42,29 @@ using namespace llvm;
 
 STATISTIC(NumTailCalls, "Number of tail calls");
 
+enum MaterializeFPImm {
+  NoMaterializeFPImm,
+  MaterializeFPImm1Ins,
+  MaterializeFPImm2Ins,
+  MaterializeFPImm3Ins,
+  MaterializeFPImm4Ins
+};
+
+static cl::opt<MaterializeFPImm> MaterializeFPImmInsNum(
+    "loongarch-materialize-float-imm", cl::Hidden,
+    cl::desc("Maximum number of instructions used when materializing "
+             "floating-point immediates (default = 2)"),
+    cl::init(MaterializeFPImm2Ins),
+    cl::values(clEnumValN(NoMaterializeFPImm, "0", "Use constant pool"),
+               clEnumValN(MaterializeFPImm1Ins, "1",
+                          "Materialize FP immediate within 1 instruction"),
+               clEnumValN(MaterializeFPImm2Ins, "2",
+                          "Materialize FP immediate within 2 instructions"),
+               clEnumValN(MaterializeFPImm3Ins, "3",
+                          "Materialize FP immediate within 3 instructions"),
+               clEnumValN(MaterializeFPImm4Ins, "4",
+                          "Materialize FP immediate within 4 instructions")));
+
 static cl::opt<bool> ZeroDivCheck("loongarch-check-zero-division", cl::Hidden,
                                   cl::desc("Trap on integer division by zero."),
                                   cl::init(false));
@@ -572,7 +596,7 @@ SDValue LoongArchTargetLowering::lowerConstantFP(SDValue Op,
     return SDValue();
 
   // If lsx enabled, use cheaper 'vldi' instruction if possible.
-  if (Subtarget.hasExtLSX() && isFPImmVLDILegal(FPVal, VT))
+  if (isFPImmVLDILegal(FPVal, VT))
     return SDValue();
 
   // Construct as integer, and move to float register.
@@ -590,10 +614,18 @@ SDValue LoongArchTargetLowering::lowerConstantFP(SDValue Op,
                        DL, VT, NewVal);
   }
   case MVT::f64: {
+    // If more than MaterializeFPImmInsNum instructions will be used to
+    // generate the INTVal, fallback to use floating point load from the
+    // constant pool.
+    auto Seq = LoongArchMatInt::generateInstSeq(INTVal.getSExtValue());
+    if (Seq.size() > MaterializeFPImmInsNum && !FPVal.isExactlyValue(+1.0))
+      return SDValue();
+
     if (Subtarget.is64Bit()) {
       SDValue NewVal = DAG.getConstant(INTVal, DL, MVT::i64);
       return DAG.getNode(LoongArchISD::MOVGR2FR_D, DL, VT, NewVal);
     }
+
     SDValue Lo = DAG.getConstant(INTVal.trunc(32), DL, MVT::i32);
     SDValue Hi = DAG.getConstant(INTVal.lshr(32).trunc(32), DL, MVT::i32);
     return DAG.getNode(LoongArchISD::MOVGR2FR_D_LO_HI, DL, VT, Lo, Hi);

llvm/test/CodeGen/LoongArch/calling-conv-ilp32d.ll

@@ -72,21 +72,17 @@ define i32 @caller_double_in_gpr_exhausted_fprs() nounwind {
 ; CHECK-NEXT:    lu12i.w $a0, 262144
 ; CHECK-NEXT:    fmov.d $fa1, $fa7
 ; CHECK-NEXT:    movgr2frh.w $fa1, $a0
-; CHECK-NEXT:    lu12i.w $a0, 262272
-; CHECK-NEXT:    fmov.d $fa2, $fa7
-; CHECK-NEXT:    movgr2frh.w $fa2, $a0
 ; CHECK-NEXT:    lu12i.w $a0, 262400
 ; CHECK-NEXT:    fmov.d $fa3, $fa7
 ; CHECK-NEXT:    movgr2frh.w $fa3, $a0
-; CHECK-NEXT:    lu12i.w $a0, 262464
-; CHECK-NEXT:    fmov.d $fa4, $fa7
-; CHECK-NEXT:    movgr2frh.w $fa4, $a0
-; CHECK-NEXT:    lu12i.w $a0, 262528
-; CHECK-NEXT:    fmov.d $fa5, $fa7
-; CHECK-NEXT:    movgr2frh.w $fa5, $a0
-; CHECK-NEXT:    lu12i.w $a0, 262592
-; CHECK-NEXT:    fmov.d $fa6, $fa7
-; CHECK-NEXT:    movgr2frh.w $fa6, $a0
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI3_0)
+; CHECK-NEXT:    fld.d $fa2, $a0, %pc_lo12(.LCPI3_0)
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI3_1)
+; CHECK-NEXT:    fld.d $fa4, $a0, %pc_lo12(.LCPI3_1)
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI3_2)
+; CHECK-NEXT:    fld.d $fa5, $a0, %pc_lo12(.LCPI3_2)
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI3_3)
+; CHECK-NEXT:    fld.d $fa6, $a0, %pc_lo12(.LCPI3_3)
 ; CHECK-NEXT:    lu12i.w $a0, 262656
 ; CHECK-NEXT:    movgr2frh.w $fa7, $a0
 ; CHECK-NEXT:    lu12i.w $a1, 262688
@@ -138,23 +134,19 @@ define i32 @caller_double_on_stack_exhausted_fprs_gprs() nounwind {
 ; CHECK-NEXT:    lu12i.w $a0, 262144
 ; CHECK-NEXT:    fmov.d $fa1, $fa7
 ; CHECK-NEXT:    movgr2frh.w $fa1, $a0
-; CHECK-NEXT:    lu12i.w $a0, 262272
-; CHECK-NEXT:    fmov.d $fa2, $fa7
-; CHECK-NEXT:    movgr2frh.w $fa2, $a0
 ; CHECK-NEXT:    lu12i.w $a0, 262400
 ; CHECK-NEXT:    fmov.d $fa3, $fa7
 ; CHECK-NEXT:    movgr2frh.w $fa3, $a0
-; CHECK-NEXT:    lu12i.w $a0, 262464
-; CHECK-NEXT:    fmov.d $fa4, $fa7
-; CHECK-NEXT:    movgr2frh.w $fa4, $a0
-; CHECK-NEXT:    lu12i.w $a0, 262528
-; CHECK-NEXT:    fmov.d $fa5, $fa7
-; CHECK-NEXT:    movgr2frh.w $fa5, $a0
-; CHECK-NEXT:    lu12i.w $a0, 262592
-; CHECK-NEXT:    fmov.d $fa6, $fa7
-; CHECK-NEXT:    movgr2frh.w $fa6, $a0
 ; CHECK-NEXT:    lu12i.w $a0, 262656
 ; CHECK-NEXT:    movgr2frh.w $fa7, $a0
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI5_0)
+; CHECK-NEXT:    fld.d $fa2, $a0, %pc_lo12(.LCPI5_0)
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI5_1)
+; CHECK-NEXT:    fld.d $fa4, $a0, %pc_lo12(.LCPI5_1)
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI5_2)
+; CHECK-NEXT:    fld.d $fa5, $a0, %pc_lo12(.LCPI5_2)
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI5_3)
+; CHECK-NEXT:    fld.d $fa6, $a0, %pc_lo12(.LCPI5_3)
 ; CHECK-NEXT:    lu12i.w $a1, 262688
 ; CHECK-NEXT:    lu12i.w $a3, 262720
 ; CHECK-NEXT:    lu12i.w $a5, 262752