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Revert "[Mips] Fix atomic min/max generate mips4 instructions when compiling for mips2" (#159495)
Reverts #149983
1 parent ddb9c78 commit ddf0f6f

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2 files changed

+25
-709
lines changed

2 files changed

+25
-709
lines changed

‎llvm/lib/Target/Mips/MipsExpandPseudo.cpp‎

Lines changed: 25 additions & 188 deletions
Original file line numberDiff line numberDiff line change
@@ -432,44 +432,23 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
432432
Register OldVal = I->getOperand(6).getReg();
433433
Register BinOpRes = I->getOperand(7).getReg();
434434
Register StoreVal = I->getOperand(8).getReg();
435-
bool NoMovnInstr = (IsMin || IsMax) && !STI->hasMips4() && !STI->hasMips32();
436435

437436
const BasicBlock *LLVM_BB = BB.getBasicBlock();
438437
MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
439-
MachineBasicBlock *loop1MBB;
440-
MachineBasicBlock *loop2MBB;
441-
if (NoMovnInstr) {
442-
loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
443-
loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
444-
}
445438
MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
446439
MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
447440
MachineFunction::iterator It = ++BB.getIterator();
448441
MF->insert(It, loopMBB);
449-
if (NoMovnInstr) {
450-
MF->insert(It, loop1MBB);
451-
MF->insert(It, loop2MBB);
452-
}
453442
MF->insert(It, sinkMBB);
454443
MF->insert(It, exitMBB);
455444

456445
exitMBB->splice(exitMBB->begin(), &BB, std::next(I), BB.end());
457446
exitMBB->transferSuccessorsAndUpdatePHIs(&BB);
458447

459448
BB.addSuccessor(loopMBB, BranchProbability::getOne());
460-
if (NoMovnInstr) {
461-
loopMBB->addSuccessor(loop1MBB);
462-
loopMBB->addSuccessor(loop2MBB);
463-
} else {
464-
loopMBB->addSuccessor(sinkMBB);
465-
loopMBB->addSuccessor(loopMBB);
466-
}
449+
loopMBB->addSuccessor(sinkMBB);
450+
loopMBB->addSuccessor(loopMBB);
467451
loopMBB->normalizeSuccProbs();
468-
if (NoMovnInstr) {
469-
loop1MBB->addSuccessor(loop2MBB);
470-
loop2MBB->addSuccessor(loopMBB);
471-
loop2MBB->addSuccessor(exitMBB, BranchProbability::getOne());
472-
}
473452

474453
BuildMI(loopMBB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
475454
if (IsNand) {
@@ -546,7 +525,7 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
546525
BuildMI(loopMBB, DL, TII->get(OR), BinOpRes)
547526
.addReg(BinOpRes)
548527
.addReg(Scratch4);
549-
} else if (STI->hasMips4() || STI->hasMips32()) {
528+
} else {
550529
// max: move BinOpRes, StoreVal
551530
// movn BinOpRes, Incr, Scratch4, BinOpRes
552531
// min: move BinOpRes, StoreVal
@@ -558,59 +537,12 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
558537
.addReg(Incr)
559538
.addReg(Scratch4)
560539
.addReg(BinOpRes);
561-
} else {
562-
// if min:
563-
// loopMBB: move BinOpRes, StoreVal
564-
// beq Scratch4, 0, loop1MBB
565-
// j loop2MBB
566-
// loop1MBB: move BinOpRes, Incr
567-
// loop2MBB: and BinOpRes, BinOpRes, Mask
568-
// and StoreVal, OlddVal, Mask2
569-
// or StoreVal, StoreVal, BinOpRes
570-
// StoreVal<tied1> = sc StoreVal, 0(Ptr)
571-
// beq StoreVal, zero, loopMBB
572-
//
573-
// if max:
574-
// loopMBB: move BinOpRes, Incr
575-
// beq Scratch4, 0, loop1MBB
576-
// j loop2MBB
577-
// loop1MBB: move BinOpRes, StoreVal
578-
// loop2MBB: and BinOpRes, BinOpRes, Mask
579-
// and StoreVal, OlddVal, Mask2
580-
// or StoreVal, StoreVal, BinOpRes
581-
// StoreVal<tied1> = sc StoreVal, 0(Ptr)
582-
// beq StoreVal, zero, loopMBB
583-
if (IsMin) {
584-
BuildMI(loopMBB, DL, TII->get(OR), BinOpRes)
585-
.addReg(StoreVal)
586-
.addReg(Mips::ZERO);
587-
BuildMI(loop1MBB, DL, TII->get(OR), BinOpRes)
588-
.addReg(Incr)
589-
.addReg(Mips::ZERO);
590-
} else {
591-
BuildMI(loopMBB, DL, TII->get(OR), BinOpRes)
592-
.addReg(Incr)
593-
.addReg(Mips::ZERO);
594-
BuildMI(loop1MBB, DL, TII->get(OR), BinOpRes)
595-
.addReg(StoreVal)
596-
.addReg(Mips::ZERO);
597-
}
598-
BuildMI(loopMBB, DL, TII->get(BEQ))
599-
.addReg(Scratch4)
600-
.addReg(Mips::ZERO)
601-
.addMBB(loop1MBB);
602-
BuildMI(loopMBB, DL, TII->get(Mips::B)).addMBB(loop2MBB);
603540
}
604541

605542
// and BinOpRes, BinOpRes, Mask
606-
if (NoMovnInstr)
607-
BuildMI(loop2MBB, DL, TII->get(Mips::AND), BinOpRes)
608-
.addReg(BinOpRes)
609-
.addReg(Mask);
610-
else
611-
BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes)
612-
.addReg(BinOpRes)
613-
.addReg(Mask);
543+
BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes)
544+
.addReg(BinOpRes)
545+
.addReg(Mask);
614546

615547
} else if (!IsSwap) {
616548
// <binop> binopres, oldval, incr2
@@ -632,37 +564,14 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
632564
// or StoreVal, StoreVal, BinOpRes
633565
// StoreVal<tied1> = sc StoreVal, 0(Ptr)
634566
// beq StoreVal, zero, loopMBB
635-
if (NoMovnInstr) {
636-
BuildMI(loop2MBB, DL, TII->get(Mips::AND), StoreVal)
637-
.addReg(OldVal)
638-
.addReg(Mask2);
639-
BuildMI(loop2MBB, DL, TII->get(Mips::OR), StoreVal)
640-
.addReg(StoreVal)
641-
.addReg(BinOpRes);
642-
BuildMI(loop2MBB, DL, TII->get(SC), StoreVal)
643-
.addReg(StoreVal)
644-
.addReg(Ptr)
645-
.addImm(0);
646-
BuildMI(loop2MBB, DL, TII->get(BEQ))
647-
.addReg(StoreVal)
648-
.addReg(Mips::ZERO)
649-
.addMBB(loopMBB);
650-
} else {
651-
BuildMI(loopMBB, DL, TII->get(Mips::AND), StoreVal)
652-
.addReg(OldVal)
653-
.addReg(Mask2);
654-
BuildMI(loopMBB, DL, TII->get(Mips::OR), StoreVal)
655-
.addReg(StoreVal)
656-
.addReg(BinOpRes);
657-
BuildMI(loopMBB, DL, TII->get(SC), StoreVal)
658-
.addReg(StoreVal)
659-
.addReg(Ptr)
660-
.addImm(0);
661-
BuildMI(loopMBB, DL, TII->get(BEQ))
662-
.addReg(StoreVal)
663-
.addReg(Mips::ZERO)
664-
.addMBB(loopMBB);
665-
}
567+
BuildMI(loopMBB, DL, TII->get(Mips::AND), StoreVal)
568+
.addReg(OldVal).addReg(Mask2);
569+
BuildMI(loopMBB, DL, TII->get(Mips::OR), StoreVal)
570+
.addReg(StoreVal).addReg(BinOpRes);
571+
BuildMI(loopMBB, DL, TII->get(SC), StoreVal)
572+
.addReg(StoreVal).addReg(Ptr).addImm(0);
573+
BuildMI(loopMBB, DL, TII->get(BEQ))
574+
.addReg(StoreVal).addReg(Mips::ZERO).addMBB(loopMBB);
666575

667576
// sinkMBB:
668577
// and maskedoldval1,oldval,mask
@@ -691,10 +600,6 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
691600

692601
LivePhysRegs LiveRegs;
693602
computeAndAddLiveIns(LiveRegs, *loopMBB);
694-
if (NoMovnInstr) {
695-
computeAndAddLiveIns(LiveRegs, *loop1MBB);
696-
computeAndAddLiveIns(LiveRegs, *loop2MBB);
697-
}
698603
computeAndAddLiveIns(LiveRegs, *sinkMBB);
699604
computeAndAddLiveIns(LiveRegs, *exitMBB);
700605

@@ -841,41 +746,20 @@ bool MipsExpandPseudo::expandAtomicBinOp(MachineBasicBlock &BB,
841746
llvm_unreachable("Unknown pseudo atomic!");
842747
}
843748

844-
bool NoMovnInstr = (IsMin || IsMax) && !STI->hasMips4() && !STI->hasMips32();
845749
const BasicBlock *LLVM_BB = BB.getBasicBlock();
846750
MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
847-
MachineBasicBlock *loop1MBB;
848-
MachineBasicBlock *loop2MBB;
849-
if (NoMovnInstr) {
850-
loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
851-
loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
852-
}
853751
MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
854752
MachineFunction::iterator It = ++BB.getIterator();
855753
MF->insert(It, loopMBB);
856-
if (NoMovnInstr) {
857-
MF->insert(It, loop1MBB);
858-
MF->insert(It, loop2MBB);
859-
}
860754
MF->insert(It, exitMBB);
861755

862756
exitMBB->splice(exitMBB->begin(), &BB, std::next(I), BB.end());
863757
exitMBB->transferSuccessorsAndUpdatePHIs(&BB);
864758

865759
BB.addSuccessor(loopMBB, BranchProbability::getOne());
866-
if (NoMovnInstr) {
867-
loopMBB->addSuccessor(loop1MBB);
868-
loopMBB->addSuccessor(loop2MBB);
869-
} else {
870-
loopMBB->addSuccessor(exitMBB);
871-
loopMBB->addSuccessor(loopMBB);
872-
}
760+
loopMBB->addSuccessor(exitMBB);
761+
loopMBB->addSuccessor(loopMBB);
873762
loopMBB->normalizeSuccProbs();
874-
if (NoMovnInstr) {
875-
loop1MBB->addSuccessor(loop2MBB);
876-
loop2MBB->addSuccessor(loopMBB);
877-
loop2MBB->addSuccessor(exitMBB, BranchProbability::getOne());
878-
}
879763

880764
BuildMI(loopMBB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
881765
assert((OldVal != Ptr) && "Clobbered the wrong ptr reg!");
@@ -918,7 +802,7 @@ bool MipsExpandPseudo::expandAtomicBinOp(MachineBasicBlock &BB,
918802
BuildMI(loopMBB, DL, TII->get(OR), Scratch)
919803
.addReg(Scratch)
920804
.addReg(Scratch2);
921-
} else if (STI->hasMips4() || STI->hasMips32()) {
805+
} else {
922806
// max: move Scratch, OldVal
923807
// movn Scratch, Incr, Scratch2, Scratch
924808
// min: move Scratch, OldVal
@@ -930,38 +814,6 @@ bool MipsExpandPseudo::expandAtomicBinOp(MachineBasicBlock &BB,
930814
.addReg(Incr)
931815
.addReg(Scratch2)
932816
.addReg(Scratch);
933-
} else {
934-
// if min:
935-
// loopMBB: move Scratch, OldVal
936-
// beq Scratch2_32, 0, loop1MBB
937-
// j loop2MBB
938-
// loop1MBB: move Scratch, Incr
939-
// loop2MBB: sc $2, 0($4)
940-
// beqz $2, $BB0_1
941-
// nop
942-
//
943-
// if max:
944-
// loopMBB: move Scratch, Incr
945-
// beq Scratch2_32, 0, loop1MBB
946-
// j loop2MBB
947-
// loop1MBB: move Scratch, OldVal
948-
// loop2MBB: sc $2, 0($4)
949-
// beqz $2, $BB0_1
950-
// nop
951-
if (IsMin) {
952-
BuildMI(loopMBB, DL, TII->get(OR), Scratch).addReg(OldVal).addReg(ZERO);
953-
BuildMI(loop1MBB, DL, TII->get(OR), Scratch).addReg(Incr).addReg(ZERO);
954-
} else {
955-
BuildMI(loopMBB, DL, TII->get(OR), Scratch).addReg(Incr).addReg(ZERO);
956-
BuildMI(loop1MBB, DL, TII->get(OR), Scratch)
957-
.addReg(OldVal)
958-
.addReg(ZERO);
959-
}
960-
BuildMI(loopMBB, DL, TII->get(BEQ))
961-
.addReg(Scratch2_32)
962-
.addReg(ZERO)
963-
.addMBB(loop1MBB);
964-
BuildMI(loopMBB, DL, TII->get(Mips::B)).addMBB(loop2MBB);
965817
}
966818

967819
} else if (Opcode) {
@@ -977,35 +829,20 @@ bool MipsExpandPseudo::expandAtomicBinOp(MachineBasicBlock &BB,
977829
BuildMI(loopMBB, DL, TII->get(OR), Scratch).addReg(Incr).addReg(ZERO);
978830
}
979831

980-
if (NoMovnInstr) {
981-
BuildMI(loop2MBB, DL, TII->get(SC), Scratch)
982-
.addReg(Scratch)
983-
.addReg(Ptr)
984-
.addImm(0);
985-
BuildMI(loop2MBB, DL, TII->get(BEQ))
986-
.addReg(Scratch)
987-
.addReg(ZERO)
988-
.addMBB(loopMBB);
989-
} else {
990-
BuildMI(loopMBB, DL, TII->get(SC), Scratch)
991-
.addReg(Scratch)
992-
.addReg(Ptr)
993-
.addImm(0);
994-
BuildMI(loopMBB, DL, TII->get(BEQ))
995-
.addReg(Scratch)
996-
.addReg(ZERO)
997-
.addMBB(loopMBB);
998-
}
832+
BuildMI(loopMBB, DL, TII->get(SC), Scratch)
833+
.addReg(Scratch)
834+
.addReg(Ptr)
835+
.addImm(0);
836+
BuildMI(loopMBB, DL, TII->get(BEQ))
837+
.addReg(Scratch)
838+
.addReg(ZERO)
839+
.addMBB(loopMBB);
999840

1000841
NMBBI = BB.end();
1001842
I->eraseFromParent();
1002843

1003844
LivePhysRegs LiveRegs;
1004845
computeAndAddLiveIns(LiveRegs, *loopMBB);
1005-
if (!STI->hasMips4() && !STI->hasMips32()) {
1006-
computeAndAddLiveIns(LiveRegs, *loop1MBB);
1007-
computeAndAddLiveIns(LiveRegs, *loop2MBB);
1008-
}
1009846
computeAndAddLiveIns(LiveRegs, *exitMBB);
1010847

1011848
return true;

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