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22 | 22 | #include "AMDKernelCodeT.h" |
23 | 23 | #include "GCNSubtarget.h" |
24 | 24 | #include "MCTargetDesc/AMDGPUInstPrinter.h" |
25 | | -#include "MCTargetDesc/AMDGPUMCKernelDescriptor.h" |
26 | 25 | #include "MCTargetDesc/AMDGPUTargetStreamer.h" |
27 | 26 | #include "R600AsmPrinter.h" |
28 | 27 | #include "SIMachineFunctionInfo.h" |
@@ -429,43 +428,38 @@ uint16_t AMDGPUAsmPrinter::getAmdhsaKernelCodeProperties( |
429 | 428 | return KernelCodeProperties; |
430 | 429 | } |
431 | 430 |
|
432 | | -MCKernelDescriptor |
433 | | -AMDGPUAsmPrinter::getAmdhsaKernelDescriptor(const MachineFunction &MF, |
434 | | - const SIProgramInfo &PI) const { |
| 431 | +amdhsa::kernel_descriptor_t AMDGPUAsmPrinter::getAmdhsaKernelDescriptor( |
| 432 | + const MachineFunction &MF, |
| 433 | + const SIProgramInfo &PI) const { |
435 | 434 | const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>(); |
436 | 435 | const Function &F = MF.getFunction(); |
437 | 436 | const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>(); |
438 | | - MCContext &Ctx = MF.getContext(); |
439 | 437 |
|
440 | | - MCKernelDescriptor KernelDescriptor; |
| 438 | + amdhsa::kernel_descriptor_t KernelDescriptor; |
| 439 | + memset(&KernelDescriptor, 0x0, sizeof(KernelDescriptor)); |
441 | 440 |
|
442 | 441 | assert(isUInt<32>(PI.ScratchSize)); |
443 | 442 | assert(isUInt<32>(PI.getComputePGMRSrc1(STM))); |
444 | 443 | assert(isUInt<32>(PI.getComputePGMRSrc2())); |
445 | 444 |
|
446 | | - KernelDescriptor.group_segment_fixed_size = |
447 | | - MCConstantExpr::create(PI.LDSSize, Ctx); |
448 | | - KernelDescriptor.private_segment_fixed_size = |
449 | | - MCConstantExpr::create(PI.ScratchSize, Ctx); |
| 445 | + KernelDescriptor.group_segment_fixed_size = PI.LDSSize; |
| 446 | + KernelDescriptor.private_segment_fixed_size = PI.ScratchSize; |
450 | 447 |
|
451 | 448 | Align MaxKernArgAlign; |
452 | | - KernelDescriptor.kernarg_size = MCConstantExpr::create( |
453 | | - STM.getKernArgSegmentSize(F, MaxKernArgAlign), Ctx); |
| 449 | + KernelDescriptor.kernarg_size = STM.getKernArgSegmentSize(F, MaxKernArgAlign); |
454 | 450 |
|
455 | | - KernelDescriptor.compute_pgm_rsrc1 = |
456 | | - MCConstantExpr::create(PI.getComputePGMRSrc1(STM), Ctx); |
457 | | - KernelDescriptor.compute_pgm_rsrc2 = |
458 | | - MCConstantExpr::create(PI.getComputePGMRSrc2(), Ctx); |
459 | | - KernelDescriptor.kernel_code_properties = |
460 | | - MCConstantExpr::create(getAmdhsaKernelCodeProperties(MF), Ctx); |
| 451 | + KernelDescriptor.compute_pgm_rsrc1 = PI.getComputePGMRSrc1(STM); |
| 452 | + KernelDescriptor.compute_pgm_rsrc2 = PI.getComputePGMRSrc2(); |
| 453 | + KernelDescriptor.kernel_code_properties = getAmdhsaKernelCodeProperties(MF); |
461 | 454 |
|
462 | 455 | assert(STM.hasGFX90AInsts() || CurrentProgramInfo.ComputePGMRSrc3GFX90A == 0); |
463 | | - KernelDescriptor.compute_pgm_rsrc3 = MCConstantExpr::create( |
464 | | - STM.hasGFX90AInsts() ? CurrentProgramInfo.ComputePGMRSrc3GFX90A : 0, Ctx); |
| 456 | + if (STM.hasGFX90AInsts()) |
| 457 | + KernelDescriptor.compute_pgm_rsrc3 = |
| 458 | + CurrentProgramInfo.ComputePGMRSrc3GFX90A; |
465 | 459 |
|
466 | | - KernelDescriptor.kernarg_preload = MCConstantExpr::create( |
467 | | - AMDGPU::hasKernargPreload(STM) ? Info->getNumKernargPreloadedSGPRs() : 0, |
468 | | - Ctx); |
| 460 | + if (AMDGPU::hasKernargPreload(STM)) |
| 461 | + KernelDescriptor.kernarg_preload = |
| 462 | + static_cast<uint16_t>(Info->getNumKernargPreloadedSGPRs()); |
469 | 463 |
|
470 | 464 | return KernelDescriptor; |
471 | 465 | } |
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